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PDF AD1672 Data sheet ( Hoja de datos )
| Número de pieza | AD1672 | |
| Descripción | Complete 12-Bit/ 3 MSPS Monolithic A/D Converter | |
| Fabricantes | Analog Devices | |
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a
Complete 12-Bit, 3 MSPS
Monolithic A/D Converter
AD1672
FEATURES
Single Supply
Pin Configurable Input Voltage Ranges
Power Dissipation: 240 mW
No Missing Codes Guaranteed
Differential Nonlinearity Error: 0.5 LSB
Complete: On-Chip Sample-and-Hold Amplifier and
Voltage Reference
Signal-to-Noise and Distortion Ratio: 68 dB
Spurious-Free Dynamic Range: –77 dB
Out of Range Indicator
Binary Output Data
Digital I/Os Compatible with +5 V or +3.3 V Logic
28-Pin PLCC Package
PRODUCT DESCRIPTION
The AD1672 is a monolithic, single supply 12-bit, 3 MSPS
analog-to-digital converter with an on-chip, high performance
sample-and-hold amplifier (SHA) and voltage reference. The
AD1672 uses a multistage pipelined architecture with output
error correction logic to provide 12-bit accuracy at 3 MSPS data
rates and guarantees no missing codes over the full operating
temperature range. The AD1672 combines a high performance
BiCMOS process and a novel architecture to achieve its high
performance levels.
The fast settling input SHA is equally suited for both multi-
plexed systems that switch negative to positive full-scale voltage
levels in successive channels and sampling single-channel inputs
at frequencies up to the Nyquist rate. The AD1672’s wideband
input combined with the power and cost savings over previously
available solutions will enable new designs in communications,
imaging and medical applications. The AD1672 provides both
reference output and reference input pins allowing the onboard
reference to serve as a system reference. An external reference
can also be chosen to suit the dc accuracy and temperature drift
requirements of the application. The digital output data is pre-
sented in a straight binary output format for the unipolar input
ranges of 0 V to 2.5 V and 0 V to 5.0 V. For the bipolar input
range of –2.5 V to +2.5 V, the digital output data is presented in
an offset binary format. An out-of-range (OTR) signal indicates
an overflow condition. It can be used with the most significant
bit to determine low or high overflow.
The AD1672 is packaged in a 28-pin PLCC package and is
specified for operation from –40°C to +85°C.
PRODUCT HIGHLIGHT
The AD1672 offers a complete single-chip sampling 12-bit,
3 MSPS analog-to-digital conversion function in a 28-pin
PLCC package.
The AD1672 at 240 mW consumes a fraction of the power of
presently available solutions and provides exceptional perfor-
mance relative to other monolithic solutions.
OUT OF RANGE (OTR)—The OTR output bit indicates
when the input signal is beyond the AD1672’s input range.
Ease-of-Use—The single supply AD1672 is complete with SHA
voltage reference and pin strappable input ranges. It is compat-
ible with a wide range of amplifiers.
FUNCTIONAL BLOCK DIAGRAM
AIN1 & 2
REF IN
REFCOM
NOISE
REDUCTION
2.5V REF
OUTPUT
REF
AMP
DAC
AMP
BANDGAP
REFERENCE
REFCOM
AD1672
THA
ADC DAC
THA
ADC DAC
THA
ADC DAC
THA
ADC
44 34
CORRECTION LOGIC
LATCHES
CLOCK TIMER
OUTPUT DATA
12 BITS
CLOCK INPUT
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD1672
PIN DESCRIPTION
Symbol
Pin
No. Type Name and Function
DRCOM 1
P Digital Output Driver Ground.
BIT 12 2 DO Data Bit (LSB).
BIT 2–11 3–12 DO Data Bits.
BIT 1
13 DO Data Bit (MSB).
DRVDD
14 P
+5 V Digital Output Driver Sup-
ply.
OTR
15 DO Out of Range is Active High on
the leading edge of Code 0 or the
trailing edge of Code 4096. See
Output Data Format Table V.
CLOCK 16 DI Sample Clock.
VDD
DCOM
17 P
18 P
+5 V Digital Supply.
Digital Ground.
REFCOM 19, 24 P
Analog Ground.
REFOUT 20
AO 2.5 V Reference Output
(Decouple with 1 µF ceramic
capacitor to REFCOM).
AIN1
21 AI Analog Input.
AIN2
22 AI Analog Input.
REFIN
23 AI Reference Input.
NCOMP2 25
AO Noise Compensation (Decouple
with 1 µF ceramic capacitor to
ACOM).
NCOMP1 26
AO Noise Compensation (Decouple
with 1 µF ceramic capacitor to
ACOM).
ACOM
27 P
Analog Ground.
VCC
28 P
+5 V Analog Supply.
TYPE: AI = Analog Input; DI = Digital Input; P = Power;
AO = Analog Output; DO = Digital Output.
Model
AD1672AP
ORDERING GUIDE
Temperature Range
–40°C to +85°C
PIN CONFIGURATION
Package
P-28A
4 3 2 1 28 27 26
BIT 9 5
BIT 8 6
BIT 7 7
BIT 6 8
BIT 5 9
BIT 4 10
BIT 3 11
PIN 1
IDENTIFIER
AD1672
TOP VIEW
(Not to Scale)
25 NCOMP2
24 REFCOM
23 REFIN
22 AIN2
21 AIN1
20 REFOUT
19 REFCOM
12 13 14 15 16 17 18
REV. 0
–5–
5 Page 
AD1672
REFERENCE INPUT
The nominal reference input is 2.5 V, taken with respect to
REFCOM. The reference input pin (REFIN) can be connected
to the reference output pin (REFOUT) or a standard external
+2.5 Volt reference can be selected to meet specific system re-
quirements. Figure 17 shows the AD1672’s REFIN being
driven from an external precision voltage reference such as the
REF192. If an external reference is used, REFOUT can be ef-
fectively disabled by tying it directly to the positive supply volt-
age VCC. Note that if the reference is changed during a conversion,
all three conversions in the pipeline will be invalidated.
The nominal 2.5 V reference input is rescaled to 1.25 V via a
resistor divider network as shown in Figure 18. The nominal
resistance of this resistor network is 8 kΩ. Table IV summa-
rizes various 2.5 V references for use with the AD1672 (see
REFERENCE OUTPUT section).
Table IV. Suitable 2.5 Volt References
Drift
(ppm/؇C)
Initial Accuracy
%
REF43B
REF192E
AD780B
10 (max)
5 (max)
3 (max)
0.1
0.08
0.04
+VCC
+VCC
10µF
0.1µF
AD780
VS
GND OUTPUT
REFOUT
AD1672
REFIN
1µF
Figure 17. Circuit using AD780 Optional +2.5 V
Reference Input Circuit
REFERENCE NOISE REDUCTION
Figure 18 shows the proper connection of two external 1 µF
capacitors, CNR1 and CNR2, associated with the two noise re-
duction nodes NCOMP1 and NCOMP2 (Pins 25 and 26) of
the AD1672. Although these noise reduction capacitors, CNR, are
not required for stability, the most optimum noise and distortion per-
formance will be attained with a 1 µF ceramic capacitor connected
from each Noise Reduction node to ACOM. CNR1 is associated with
the output of the DAC amp and is required for optimum dis-
tortion performance and SHA settling time. It provides a low
source impedance for signal-dependent, transient currents asso-
ciated with this node. CNR2 reduces the noise contribution from
the reference buffer amplifier.
1µF
20 REFOUT
AD1672
CNR2
1µF
CNR1
1µF
REFIN
23
REFCOM
24
4kΩ
4kΩ
NCOMP2
25
NCOMP1
26
REF
AMP
DAC
AMP
Figure 18. Reference Noise Reduction
REFERENCE OUTPUT
The AD1672 includes an onboard +2.5 V curvature compen-
sated bandgap reference that has been laser trimmed for both
absolute value and temperature drift. The reference must be
externally compensated with a capacitor of 1 µF or greater from
REFOUT to REFCOM.
The reference is specified to provide an additional load current
up to 500 µA. For large dynamic loads and/or external loads
greater than 500 µA, an external buffer amplifier or pull-up re-
sistor is required. If a pull-up resistor is used, its value should
be selected such that REFOUT will not be required to sink any
current under all operating conditions. Figure 19 illustrates the
load regulation of the reference. The power supply rejection of
the reference is better than 0.2 % of FSR at dc.
2.500
2.499
2.498
2.497
2.496
2.495
2.494
2.493
2.492
2.491
2.490
0
100 200 300 400 500 600 700 800 900 1000
LOAD CURRENT – µA
Figure 19. Reference Output Voltage vs. Load Current
DIGITAL OUTPUTS
The AD1672 output data is presented in positive true straight
binary for both the 0 V to 2.5 V and 0 V to 5 V unipolar input
ranges and positive true offset binary for the ± 2.5 V bipolar
range. Table V indicates the output data formats for the three
analog input ranges. Users requiring twos complement encoding
for the ± 2.5 V range may simply invert the MSB (Pin 13).
Table V. Output Data Format
Input Voltage Range +FS (V) –FS (V)
0 to +2.5
0 to +5.0
–2.5 to +2.5
+2.5 0.0
+5.0 0.0
+2.5 –2.5
LSB (mV)
0.610
1.22
1.22
OTR
1
0
0
DATA OUTPUTS
1111 111 1111
1111 1111 1111
1111 1111 1110
OTR
–FS+1/2 LSB
+FS –1 1/2 LSB
0 0000 0000 0001
0 0000 0000 0000
1 0000 0000 0000
–FS
–FS –1/2 LSB
+FS
+FS –1/2 LSB
Figure 20. Output Data Format
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD1672.PDF ] | |
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