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PDF AD15700 Data sheet ( Hoja de datos )
| Número de pieza | AD15700 | |
| Descripción | 1 MSPS 16-/14-Bit Analog I/O Port | |
| Fabricantes | Analog Devices | |
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1 MSPS 16-/14-Bit
Analog I/O Port
AD15700
FEATURES
16-Bit A/D Converter
1 MSPS
S/(N + D): 90 dB Typ @ 250 kHz
No Pipeline Delay
14-Bit D/A Converter
Settling Time: 1 s
S/N: 92 dB Typ
2 80 MHz Amplifiers
30 V/s Slew Rate
Rail-to-Rail Input and Output
Output Current 15 mA
2 Gain Setting Center Tapped Resistors
Resistor Ratio Tracking: 2 ppm/؇C
Unipolar Operation
SPI®/QSPI™/MICROWIRE™/DSP Compatible
132 mW Typical Power Dissipation
APPLICATIONS
Optical MEMS Mirror Control
Industrial Process Control
Data Acquisition
Instrumentation
Communication
GENERAL DESCRIPTION
The AD15700 is a precision component to interface analog input
and output channels to a digital processor. It is ideal for area-
limited applications that require maximum circuit density. The
AD15700 contains the functionality of a 16-bit, 1 MSPS charge
redistribution SAR analog-to-digital converter that operates from
a 5 V power supply. The high speed 16-bit sampling ADC incor-
porates a resistor input scaler that allows various input ranges, an
internal conversion clock, error correction circuits, and both serial
and parallel system interface ports. The AD15700 also contains a
14-bit, serial input, voltage output DAC that operates from a 5 V
supply and has a settling time of 1 ms. Two single- or split-supply
voltage feedback amplifiers with rail-to-rail input and output
characteristics featuring 80 MHz of small signal bandwidth and
10 mV/∞C offset drift provide ADC and DAC buffering capability.
The center tapped 3 kW resistors are precision resistor networks
with 2 ppm/∞C ratio tracking that provide low gain drift when
used for scaling.
The ADC, DAC, and amp functions are electrically isolated from
each other to provide maximum design flexibility. Input and
output signal conditioning circuits for the converters can be easily
configured with short interconnects under the device at the board
level. The AD15700 is available in a 10 mm CSPBGA package.
FUNCTIONAL BLOCK DIAGRAM
VDD_DAC
DGND_DAC
VREF
14-BIT DAC
CS_DAC
DIN
SCLK
CONTROL
LOGIC
14-BIT DATA LATCH
SERIAL INPUT REGISTER
COMMON
REF
REFGND
IND(4R)
INC(4R)
INB(2R)
INA(R)
INGND
VOUT2
+VS2
+IN2
–IN2
–VS2
PD
RESET
RPAD2
AD15700
1.5k⍀
1.5k⍀
4R
4R
2R
SERIAL
R PORT
SWITCHED
CAP DAC
CLOCK
SAR ADC
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
PARALLEL 16
INTERFACE
1.5k⍀ 1.5k⍀
RA2 RB2 RC2
WARP CNVST IMPULSE
DVDD
DGND
ADC
VOUT_DAC
AGND_DAC
–IN1
+IN1
+VS1
VOUT1
–VS1
RA1
RB1
RC1
RPAD1
OVDD
OGND
SER/PAR
BUSY
D[15:0]
CS_ADC
RD
OB/2C
BYTESWAP
AVDD
AGND_ADC
PRODUCT HIGHLIGHTS
1. Fast Throughput ADC.
The AD15700 incorporates a high speed, 1 MSPS, 16-bit
SAR ADC.
2. Superior ADC INL.
The 16-bit ADC has a maximum integral nonlineariy of
2.5 LSB with no missing codes.
3. Two Precision Resistor Networks with 2 ppm/∞C Ratio
Tracking for Gain Setting.
4. Low Power Consumption.
Typically 132 mW at maximum performance levels.
5. Industrial Temperature Range: –40∞C to +85∞C.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD15700
Table II. Serial Clock Timings in Master Read after Convert
DIVSCLK[1]
DIVSCLK[0]
SYNC to SCLK First Edge Delay Minimum
Internal SCLK Period Minimum
Internal SCLK Period Maximum
Internal SCLK HIGH Minimum
Internal SCLK LOW Minimum
SDOUT Valid Setup Time Minimum
SDOUT Valid Hold Time Minimum
SCLK Last Edge to SYNC Delay Minimum
BUSY HIGH Width Maximum (Warp)
BUSY HIGH Width Maximum (Normal)
BUSY HIGH Width Maximum (Impulse)
0011
Symbol 0 1 0 1 Unit
t18 4 20 20 20 ns
t19 25 50 100 200 ns
t19 40 70 140 280 ns
t20 15 25 50 100 ns
t21 9 24 49 99 ns
t22 4.5 22 22 22 ns
t23 2 4 30 89 ns
t24 3 60 140 300 ns
t28 1.5 2 3 5.25 ms
t28
1.75 2.25 3.25 5.5
ms
t28 2 2.5 3.5 5.75 ms
1.6mA IOL
TO OUTPUT
PIN
CL
60pF
500mA
IOH
1.4V
IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing, SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
2V
tDELAY
2V
0.8V
tDELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
REV. A
–5–
5 Page 
AD15700
ADC PIN FUNCTION DESCRIPTIONS (See Pinout, page 42)
Pin No.
H9, J8,
J9, M12
M6
L7
Mnemonic
AGND_ADC
AVDD
BYTESWAP
L8 OB/2C
M7 WARP
L9 IMPULSE
M8 SER/PAR
M9, L10 D[0:1]
M10, L11 D[2:3] or
DIVSCLK[0:1]
M11
D[4] or EXT/INT
L12 D[5] or INVSYNC
K11 D[6] or INVSCLK
K12 D[7] or RDC/SDIN
J10 OGND
J11 OVDD
J12 DVDD
Type Description
P Analog Power Ground Pin
P
DI
DI
DI
DI
DI
DO
DI/O
DI/O
DI/O
DI/O
DI/O
P
P
P
Input Analog Power Pin. Nominally 5 V.
Parallel Mode Selection (8-/16-Bit). When LOW, the LSB is output on D[7:0] and the MSB
is output on D[15:8]. When HIGH, the LSB is output on D[15:8] and the MSB is
output on D[7:0].
Straight Binary/Binary Twos Complement. When OB/2C is HIGH, the digital output
is straight binary; when LOW, the MSB is inverted, resulting in a twos complement
output from its internal shift register.
Mode Selection. When HIGH and IMPULSE LOW, this input selects the fastest mode,
the maximum throughput is achievable, and a minimum conversion rate must be applied
in order to guarantee full specified accuracy. When LOW, full accuracy is maintained
independent of the minimum conversion rate.
Mode Selection. When HIGH and WARP LOW, this input selects a reduced power mode.
In this mode, the power dissipation is approximately proportional to the sampling rate.
Serial/Parallel Selection Input. When LOW, the Parallel Port is selected; when HIGH,
the Serial Interface Mode is selected and some bits of the DATA bus are used as a
serial port.
Bit 0 and Bit 1 of the Parallel Port Data Output Bus. When SER/PAR is HIGH, these
outputs are in high impedance.
When SER/PAR is HIGH, EXT/INT is LOW and RDC/SDIN is LOW, which is the
serial master read DIVSCLK[0:1] after Convert Mode. These inputs, part of the Serial
Port, are used to slow down, if desired, the internal serial clock that clocks the data output.
In the other serial modes, these inputs are not used.
When SER/PAR is LOW, this output is used as Bit 4 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used as a digital
select input for choosing the internal or an external data clock, called, respectively, Master
and Slave Mode. With EXT/INT tied LOW, the internal clock is selected on SCLK
output. With EXT/INT set to a logic HIGH, output data is synchronized to an external
clock signal connected to the SCLK input and the external clock is gated by CS_ADC.
When SER/PAR is LOW, this output is used as Bit 5 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to select the
active state of the SYNC signal. When LOW, SYNC is active HIGH. When HIGH,
SYNC is active LOW.
When SER/PAR is LOW, this output is used as Bit 6 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the Serial Port, is used to invert the
SCLK signal. It is active in both Master and Slave Mode.
When SER/PAR is LOW, this output is used as Bit 7 of the Parallel Port Data Output
Bus. When SER/PAR is HIGH, this input, part of the serial port, is used as either an
external data input or a read mode selection input, depending on the state of EXT/INT.
When EXT/INT is HIGH, RDC/SDIN could be used as a data input to daisy-chain
the conversion results from two or more ADCs onto a single SDOUT line. The digital
data level on SDIN is output on DATA with a delay of 16 SCLK periods after the
initiation of the read sequence. When EXT/INT is LOW, RDC/SDIN is used to select
the read mode. When RDC/SDIN is HIGH, the previous data is output on SDOUT
during conversion. When RDC/SDIN is LOW, the data can be output on SDOUT
only when the conversion is complete.
Input/Output Interface Digital Power Ground
Input/Output Interface Digital Power. Nominally at the same supply as the supply of
the host interface (5 V or 3.3 V).
Digital Power. Nominally at 5 V.
REV. A
–11–
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