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Intersil Corporation - Radiation Hardened Octal Three-State Transparent Latch

Numéro de référence ACTS573HMSR
Description Radiation Hardened Octal Three-State Transparent Latch
Fabricant Intersil Corporation 
Logo Intersil Corporation 





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ACTS573HMSR fiche technique
ACTS573MS
January 1996
Radiation Hardened Octal
Three-State Transparent Latch
Features
• Devices QML Qualified in Accordance with MIL-PRF-38535
• Detailed Electrical and Screening Requirements are Contained in
SMD# 5962-96725 and Intersil’s QM Plan
• 1.25 Micron Radiation Hardened SOS CMOS
• Total Dose . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . >300K RAD (Si)
• Single Event Upset (SEU) Immunity: <1 x 10-10 Errors/Bit/Day
(Typ)
• SEU LET Threshold . . . . . . . . . . . . . . . . . . . . . . . >100 MEV-cm2/mg
• Dose Rate Upset . . . . . . . . . . . . . . . . >1011 RAD (Si)/s, 20ns Pulse
• Dose Rate Survivability . . . . . . . . . . . >1012 RAD (Si)/s, 20ns Pulse
• Latch-Up Free Under Any Conditions
• Military Temperature Range . . . . . . . . . . . . . . . . . . -55oC to +125oC
• Significant Power Reduction Compared to ALSTTL Logic
• DC Operating Voltage Range . . . . . . . . . . . . . . . . . . . . 4.5V to 5.5V
• Input Logic Levels
- VIL = 0.8V Max
- VIH = VCC/2 Min
• Input Current 1µA at VOL, VOH
• Fast Propagation Delay . . . . . . . . . . . . . . . . 18ns (Max), 12ns (Typ)
Description
The Intersil ACTS573MS is a Radiation Hardened Octal Transparent
Latch with an active low output enable. The outputs are transparent to
the inputs when the latch enable (LE) is High. When the latch goes low
the data is latched. The output enable controls the three-state outputs.
When the output enable pins (OE) are high the output is in a high
impedance state. The latch operation is independent of the state of
output enable.
The ACTS573MS utilizes advanced CMOS/SOS technology to achieve
high-speed operation. This device is a member of a radiation hardened,
high-speed, CMOS/SOS Logic family.
The ACTS573MS is supplied in a 20 lead Ceramic Flatpack (K suffix) or
a Ceramic Dual-In-Line package (D suffix).
Pinouts
20 LEAD CERAMIC DUAL-IN-LINE
MIL-STD-1835 DESIGNATOR,
CDIP2-T20, LEAD FINISH C
TOP VIEW
OE 1
D0 2
D1 3
D2 4
D3 5
D4 6
D5 7
D6 8
D7 9
GND 10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
20 LEAD CERAMIC FLATPACK
MIL-STD-1835 DESIGNATOR,
CDFP4-F20, LEAD FINISH C
TOP VIEW
OE
D0
D1
D2
D3
D4
D5
D6
D7
GND
1
2
3
4
5
6
7
8
9
10
20 VCC
19 Q0
18 Q1
17 Q2
16 Q3
15 Q4
14 Q5
13 Q6
12 Q7
11 LE
Ordering Information
PART NUMBER
5962F9672501VRC
5962F9672501VXC
ACTS573D/Sample
ACTS573K/Sample
ACTS573HMSR
TEMPERATURE RANGE
-55oC to +125oC
-55oC to +125oC
25oC
25oC
25oC
SCREENING LEVEL
MIL-PRF-38535 Class V
MIL-PRF-38535 Class V
Sample
Sample
Die
PACKAGE
20 Lead SBDIP
20 Lead Ceramic Flatpack
20 Lead SBDIP
20 Lead Ceramic Flatpack
Die
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
1-888-INTERSIL or 321-724-7143 | Copyright © Intersil Corporation 1999
1
Spec Number 518892
File Number 4092

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