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PDF AD561 Data sheet ( Hoja de datos )
| Número de pieza | AD561 | |
| Descripción | Low Cost 10-Bit Monolithic D/A Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Low Cost 10-Bit
Monolithic D/A Converter
AD561
FEATURES
Complete Current Output Converter
High Stability Buried Zener Reference
Laser Trimmed to High Accuracy (1/4 LSB Max Error,
AD561K, T)
Trimmed Output Application Resistors for 0 V to +10 V,
؎5 V Ranges
Fast Settling – 250 ns to 1/2 LSB
Guaranteed Monotonicity Over Full Operating
Temperature Range
TTL/DTL and CMOS Compatible (Positive True Logic)
Single Chip Monolithic Construction
Available in Chip Form
MlL-STD-883-Compliant Versions Available
PRODUCT DESCRIPTION
The AD561 is an integrated circuit 10-bit digital-to-analog
converter combined with a high stability voltage reference
fabricated on a single monolithic chip. Using ten precision high-
speed current-steering switches, a control amplifier, voltage
reference, and laser-trimmed thin-film SiCr resistor network,
the device produces a fast, accurate analog output current.
Laser trimmed output application resistors are also included to
facilitate accurate, stable current-to-voltage conversion; they are
trimmed to 0.1% accuracy, thus eliminating external trimmers
in many situations.
Several important technologies combine to make the AD561 the
most accurate and most stable 10-bit DAC available. The low
temperature coefficient, high stability thin-film network is
trimmed at the wafer level by a fine resolution laser system to
0.01% typical linearity. This results in an accuracy specification
of ± 1/4 LSB max for the K and T versions, and 1/2 LSB max
for the J and S versions.
The AD561 also incorporates a low noise, high stability
subsurface zener diode to produce a reference voltage with
excellent long term stability and temperature cycle characteris-
tics, which challenge the best discrete Zener references. A
temperature compensation circuit is laser-trimmed to allow
custom correction of the temperature coefficient of each device.
This results in a typical full-scale temperature coefficient of
15 ppm/°C; the TC is tested and guaranteed to 30 ppm/°C max
for the K and T versions, 60 ppm/°C max for the S, and
80 ppm/°C for the J.
The AD561 is available in four performance grades. The
AD561J and K are specified for use over the 0°C to +70°C
temperature range and are available in either a 16-pin
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
FUNCTIONAL BLOCK DIAGRAM
TO-116
hermetically-sealed ceramic DIP or a 16-pin molded plastic
DIP. The AD561S and T grades are specified for the –55°C to
+125°C range and are available in the ceramic package.
PRODUCT HIGHLIGHTS
1. Advanced monolithic processing and laser trimming at the
wafer level have made the AD561 the most accurate 10-bit
converter available, while keeping costs consistent with large
volume integrated circuit production. The AD561K and T
have 1/4 LSB max relative accuracy and 1/2 LSB max
differential nonlinearity. The low TC R-2R ladder guaran-
tees that all AD561 units will be monotonic over the entire
operating temperature range.
2. Digital system interfacing is simplified by the use of a
positive true straight binary code. The digital input voltage
threshold is a function of the positive supply level; connect-
ing VCC to the digital logic supply automatically sets the
threshold to the proper level for the logic family being used.
Logic sink current requirement is only 25 µA.
3. The high speed current steering switches are designed to settle
in less than 250 ns for the worst case digital code transition.
This allows construction of successive-approximation A/D
converters in the 3 µs to 5 µs range.
4. The AD561 has an output voltage compliance range from
–2 V to +10 V, allowing direct current-to-voltage conversion
with just an output resistor, omitting the op amp. The 40 MΩ
open collector output impedance results in negligible errors
due to output leakage currents.
5. The AD561 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD561/883B data sheet for detailed
specifications.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD561
UNIPOLAR CONFIGURATION
This configuration, shown in Figure 2, will provide a unipolar
0 V to +10 V output range.
STEP I . . . ZERO ADJUST
Turn all bits OFF and adjust op amp trimmer, R1, until the
output reads 0.000 volts (1 LSB = 9.76 mV).
STEP 11. . . GAIN ADJUST
Turn all bits ON and adjust 50 Ω gain trimmer, R2, until the
output is 9.990 volts. (Full scale is adjusted to 1 LSB less than
nominal full scale of 10.000 volts.) If a 10.23 V full scale is desired
(exactly 10 mV/bit), insert a 120 Ω resistor in series with R2.
BIPOLAR CONFIGURATION
This configuration, shown in Figure 3, will provide a bipolar
output voltage from –5.000 to +4.990 volts, with positive full
scale occurring with all bits ON (all 1s).
STEP 1. . . ZERO ADJUST
Turn ON MSB only, turn OFF all other bits. Adjust 50 Ω
trimmer R3, to give 0.000 output volts. For maximum resolution
a 120 Ω resistor may be placed in parallel with R3.
STEP 11. . . GAIN ADJUST
Turn OFF all bits, adjust 50 Ω gain trimmer to give a reading of
–5.000 volts.
Please note that it is not necessary to trim the op amp to obtain
full accuracy at room temperature. In most bipolar situations,
the op amp trimmer is unnecessary unless the untrimmed offset
drift of the op amp is excessive.
؎10 VOLT BUFFERED BIPOLAR OUTPUT
The AD561 can also be connected for a ± 10 volt bipolar range
with an additional external resistor as shown in Figure 4. A
larger value trimmer is required to compensate for tolerance in
the thin film resistors, which are trimmed to match the full-scale
current. For best full scale temperature coefficient performance,
the external resistors should have a TC of –50 ppm/°C.
CIRCUIT DESCRIPTION
A simplified schematic with the essential circuit features of the
AD561 is shown in Figure 5. The voltage reference, CR1, is a
buried Zener (or subsurface breakdown diode). This device
exhibits far better all-around performance than the NPN base-
emitter reverse-breakdown diode (surface Zener), which is in
nearly universal use in integrated circuits as a voltage reference.
Greatly improved long-term stability and lower noise are the
major benefits the buried Zener derives from isolating the
breakdown point from surface stress and mobile oxide charge
effects. The nominal 7.5 volt device (including temperature
compensation circuitry) is driven by a current source to the
negative supply so the positive supply can be allowed to drop as
low as 4.5 volts. The temperature coefficient of each diode is
individually determined; this data is then used to laser trim a
compensating circuit to balance the overall TC to zero. The
typical resulting TC is 0 to ± 15 ppm/°C. The negative reference
level is inverted and scaled by A1 to give a +2.5 volt reference,
which can be driven by the low positive supply. The AD561,
packaged in the 16-pin DIP, has the +2.5 volt reference (REF
OUT) connected directly to the input of the control amplifier
(REF IN). The buffered reference is not directly available
externally except through the 2.5 kΩ bipolar offset resistor.
Figure 2. 0 V to +10 V Unipolar Voltage Output
Figure 3. ±5 V Buffered Bipolar Voltage Output
Figure 4. ±10 V Buffered Voltage Output
The 2.5 kΩ scaling resistor and control amplifier A2 then force a
1 mA reference current to flow through reference transistor Q1,
which has a relative emitter area of 8A. This is accomplished by
forcing the bottom of the ladder to the proper voltage. Since Q1
and Q2 have equal emitter areas and equal 5 kΩ emitter resistors,
Q2 also carries 1 mA. The ladder voltage drop constrains Q7
(with area 4A) to carry only 0.5 mA; Q8 carries 0.25 mA, etc.
The first four significant bit cells are exactly scaled in emitter
area to match Q1 for optimum VBE and VBE drift match, as well
as for beta match. These effects are insignificant for the lower
order bits, which account for a total of only 1/16 of full scale.
However, the 18 mV VBE difference between two matched
transistors carrying emitter currents in a ratio of 2:1 must be
corrected. This is achieved by forcing 120 µA through the
150 Ω interbase resistors. These resistors, and the R-2R ladder
resistors, are actively laser-trimmed at the wafer level to bring
total device accuracy to better than 1/4 LSB. Sufficient ratio
accuracy in the last two bits is obtained by simple emitter area
REV. A
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD561.PDF ] | |
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