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PDF AD5344 Data sheet ( Hoja de datos )
| Número de pieza | AD5344 | |
| Descripción | Parallel Interface Quad Voltage-Output 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5344 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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a 2.5 V to 5.5 V, 500 A, Parallel Interface
Quad Voltage-Output 8-/10-/12-Bit DACs
AD5334/AD5335/AD5336/AD5344*
FEATURES
AD5334: Quad 8-Bit DAC in 24-Lead TSSOP
AD5335: Quad 10-Bit DAC in 24-Lead TSSOP
AD5336: Quad 10-Bit DAC in 28-Lead TSSOP
AD5344: Quad 12-Bit DAC in 28-Lead TSSOP
Low Power Operation: 500 A @ 3 V, 600 A @ 5 V
Power-Down to 80 nA @ 3 V, 200 nA @ 5 V via PD Pin
2.5 V to 5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic by Design Over All Codes
Output Range: 0–VREF or 0–2 VREF
Power-On Reset to Zero Volts
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Parallel Data Interface
On-Chip Rail-to-Rail Output Buffer Amplifiers
Temperature Range: –40؇C to +105؇C
APPLICATIONS
Portable Battery-Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
Industrial Process Control
GENERAL DESCRIPTION
The AD5334/AD5335/AD5336/AD5344 are quad 8-, 10-, and
12-bit DACs. They operate from a 2.5 V to 5.5 V supply con-
suming just 500 µA at 3 V, and feature a power-down mode that
further reduces the current to 80 nA. These devices incorporate
an on-chip output buffer that can drive the output to both sup-
ply rails.
The AD5334/AD5335/AD5336/AD5344 have a parallel interface.
CS selects the device and data is loaded into the input registers
on the rising edge of WR.
The GAIN pin on the AD5334 and AD5336 allows the output
range to be set at 0 V to VREF or 0 V to 2 × VREF.
Input data to the DACs is double-buffered, allowing simultaneous
update of multiple DACs in a system using the LDAC pin.
On the AD5334, AD5335 and AD5336 an asynchronous CLR
input is also provided. This resets the contents of the Input
Register and the DAC Register to all zeros. These devices also
incorporate a power-on-reset circuit that ensures that the DAC
output powers on to 0 V and remains there until valid data is
written to the device.
The AD5334/AD5335/AD5336/AD5344 are available in Thin
Shrink Small Outline Packages (TSSOP).
AD5334 FUNCTIONAL BLOCK DIAGRAM
(Other Diagrams Inside)
VREFA/B
VDD
GAIN
DB... 7
DB0
CS
WR
A0
A1
POWER-ON
RESET
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INTER-
FACE
LOGIC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INPUT
DAC
REGISTER REGISTER
8-B8I-TBIT
DADCAC
AD5334
BUFFER
BUFFER
BUFFER
VOUTA
VOUTB
VOUTC
CLR
LDAC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
BUFFER
VOUTD
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
*Protected by U.S. Patent Number 5,969,657.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREFC/D
PD GND
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
GAIN
DB... 7
DB0
CS
WR
A0
A1
AD5334 FUNCTIONAL BLOCK DIAGRAM
VREFA/B
VDD
POWER-ON
RESET
AD5334
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
BUFFER
INTER-
FACE
LOGIC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
INPUT
DAC
REGISTER REGISTER
8-B8I-TBIT
DADCAC
BUFFER
BUFFER
AD5334/AD5335/AD5336/AD5344
AD5334 PIN CONFIGURATION
VOUTA
VOUTB
VOUTC
VREFC/D 1
24 CLR
VREFA/B 2
23 GAIN
VOUTA 3
22 DB7
VOUTB
VOUTC
VOUTD
GND
CS
4 21 DB6
8-BIT
5 AD5334 20 DB5
6 TOP VIEW 19 DB4
7 (Not to Scale) 18 DB3
8 17 DB2
WR 9
16 DB1
A0 10
15 DB0
A1 11
LDAC 12
14 VDD
13 PD
CLR
LDAC
INPUT
DAC
REGISTER REGISTER
8-BIT
DAC
BUFFER
VOUTD
TO ALL DACS
AND BUFFERS
POWER-DOWN
LOGIC
VREFC/D
PD GND
Pin
No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15–22
23
24
Mnemonic
VREFC/D
VREFA/B
VOUTA
VOUTB
VOUTC
VOUTD
GND
CS
WR
A0
A1
LDAC
PD
VDD
DB0–DB7
GAIN
CLR
AD5334 PIN FUNCTION DESCRIPTIONS
Function
Unbuffered Reference Input for DACs C and D.
Unbuffered Reference Input for DACs A and B.
Output of DAC A. Buffered Output with Rail-to-Rail Operation.
Output of DAC B. Buffered Output with Rail-to-Rail Operation.
Output of DAC C. Buffered Output with Rail-to-Rail Operation.
Output of DAC D. Buffered Output with Rail-to-Rail Operation.
Ground Reference Point for All Circuitry on the Part.
Active Low Chip Select Input. This is used in conjunction with WR to write data to the parallel interface.
Active Low Write Input. This is used in conjunction with CS to write data to the parallel interface.
LSB Address Pin for Selecting which DAC Is to Be Written to.
MSB Address Pin for Selecting which DAC Is to Be Written to.
Active Low Control Input that Updates the DAC Registers with the Contents of the Input Registers.
This allows all DAC outputs to be simultaneously updated.
Power-Down Pin. This active low control pin puts all DACs into power-down mode.
Power Supply Pin. This part can operate from 2.5 V to 5.5 V and the supply should be decoupled with a
10 µF capacitor in parallel with a 0.1 µF capacitor to GND.
Eight Parallel Data Inputs. DB7 is the MSB of these eight bits.
Gain Control Pin. This controls whether the output range from the DAC is 0–VREF or 0–2 VREF
Asynchronous Active Low Control Input that Clears All Input Registers and DAC Registers to Zeros.
REV. 0
–5–
5 Page 
Typical Performance Characteristics–AD5334/AD5335/AD5336/AD5344
1.0
TA = 25؇C
VDD = 5V
0.5
0
–0.5
–1.0
0
50 100 150 200 250
CODE
Figure 5. AD5334 Typical INL Plot
3
TA = 25؇C
VDD = 5V
2
1
0
–1
–2
–3
0
200 400 600 800 1000
CODE
Figure 6. AD5335 Typical INL Plot
12
TA = 25؇C
8 VDD = 5V
4
0
–4
–8
–12
0
1000
2000
CODE
3000
4000
Figure 7. AD5336 Typical INL Plot
0.3
TA = 25؇C
VDD = 5V
0.2
0.1
0
–0.1
–0.2
–0.3
0
50 100 150 200 250
CODE
Figure 8. AD5334 Typical DNL Plot
0.6
TA = 25؇C
VDD = 5V
0.4
0.2
0
–0.2
–0.4
–0.6
0
200 400 600 800 1000
CODE
Figure 9. AD5335 Typical DNL Plot
1
TA = 25؇C
VDD = 5V
0.5
0
–0.5
–1
0
1000
2000
3000
4000
CODE
Figure 10. AD5336 Typical DNL Plot
0.5
0.25
VDD = 5V
TA = 25؇C
MAX INL
MAX DNL
0
–0.25
MIN DNL
MIN INL
–0.5
0 12 345
VREF – V
Figure 11. AD5334 INL and DNL
Error vs. VREF
0.5
0.4 VDD = 5V
VREF = 2V
0.3
MAX INL
0.2
0.1 MAX DNL
0
–0.1
–0.2
MIN DNL
–0.3
–0.4
MIN INL
–0.5
؊40
0 40 80
TEMPERATURE – ؇C
120
Figure 12. AD5334 INL Error and
DNL Error vs. Temperature
1
VDD = 5V
VREF = 2V
0.5
0
–0.5
GAIN ERROR
OFFSET ERROR
–1
؊40
0 40 80
TEMPERATURE – ؇C
120
Figure 13. AD5334 Offset Error
and Gain Error vs. Temperature
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5344.PDF ] | |
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