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PDF AD5328 Data sheet ( Hoja de datos )
| Número de pieza | AD5328 | |
| Descripción | 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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2.5 V to 5.5 V Octal Voltage Output
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5308/AD5318/AD5328
FEATURES
AD5308: 8 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL, B version: ±0.75 LSB INL
AD5318: 8 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL, B version: ±3 LSB INL
AD5328: 8 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL, B version: ±12 LSB INL
Low power operation: 0.7 mA @ 3 V
Guaranteed monotonic by design over all codes
Power-down to 120 nA @ 3 V, 400 nA @ 5 V
Double-buffered input logic
Buffered/unbuffered/VDD reference input options
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
Programmability
Individual channel power-down
Simultaneous update of outputs (LDAC)
Low power, SPI-®, QSPI-™, MICROWIRE-™, and DSP-
compatible 3-wire serial interface
On-chip rail-to-rail output buffer amplifiers
Temperature range: −40°C to +125°C
Qualified for automotive applications
APPLICATIONS
Portable battery-powered instruments
Digital gain and offset adjustment
Programmable voltage and current sources
Optical networking
Automatic test equipment
Mobile communications
Programmable attenuators
Industrial process control
GENERAL DESCRIPTION
The AD5308/AD5318/AD5328 are octal 8-, 10-, and 12-bit
buffered voltage output DACs in a 16-lead TSSOP. They operate
from a single 2.5 V to 5.5 V supply, consuming 0.7 mA typical
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/μs. The AD5308/
AD5318/AD5328 use a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI, QSPI, MICROWIRE, and DSP interface
standards.
The references for the eight DACs are derived from two
reference pins (one per DAC quad). These reference inputs can
be configured as buffered, unbuffered, or VDD inputs. The parts
incorporate a power-on reset circuit, which ensures that the
DAC outputs power up to 0 V and remain there until a valid
write to the device takes place. The outputs of all DACs may be
updated simultaneously using the asynchronous LDAC input.
The parts contain a power-down feature that reduces the current
consumption of the devices to 400 nA at 5 V (120 nA at 3 V).
The eight channels of the DAC may be powered down individually.
All three parts are offered in the same pinout, which allows
users to select the resolution appropriate for their application
without redesigning their circuit board.
Rev. F
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2002–2011 Analog Devices, Inc. All rights reserved.
1 page  
AD5308/AD5318/AD5328
Parameter2
Short Circuit Current
Power-Up Time
LOGIC INPUTS6
Input Current
VIL, Input Low Voltage
VIH, Input High Voltage
Pin Capacitance
POWER REQUIREMENTS
VDD
IDD (Normal Mode)8
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
IDD (Power-Down Mode)9
VDD = 4.5 V to 5.5 V
VDD = 2.5 V to 3.6 V
A Version1
Min Typ
Max
25.0
16.0
2.5
5.0
B Version1
Min Typ
Max
25.0
16.0
2.5
5.0
Unit
mA
mA
μs
μs
1.7
3.0
2.5
1.0
0.7
±1
0.8
0.8
0.7
1.7
3.0
5.5 2.5
1.8 1.0
1.5 0.7
±1 μA
0.8 V
0.8 V
0.7 V
V
pF
5.5 V
1.8 mA
1.5 mA
0.4 1
0.12 1
0.4 1 μA
0.12 1 μA
Conditions/Comments
VDD = 5 V
VDD = 3 V
Coming out of power-down
mode, VDD = 5 V
Coming out of power-down
mode, VDD = 3 V
VDD = 5 V ± 10%
VDD = 3 V ± 10%
VDD = 2.5 V
VDD = 2.5 V to 5.5 V, TTL and
CMOS compatible
VIH = VDD and VIL = GND
All DACs in unbuffered
mode, in buffered mode
Extra current is typically x μA
per DAC; x = (5 μA +
VREF/RDAC)/4
VIH = VDD and VIL = GND
1 Temperature range (A, B version): −40°C to +125°C; typical at 25°C.
2 See the Terminology section.
3 DC specifications tested with the outputs unloaded unless stated otherwise.
4 Linearity is tested using a reduced code range: AD5308 (Code 8 to Code 255), AD5318 (Code 28 to Code 1023), and AD5328 (Code 115 to Code 4095).
5 This corresponds to x codes. x = deadband voltage/LSB size.
6 Guaranteed by design and characterization; not production tested.
7 For the amplifier output to reach its minimum voltage, offset error must be negative. For the amplifier output to reach its maximum voltage, VREF = VDD and offset plus
gain error must be positive.
8 Interface inactive. All DACs active. DAC outputs unloaded.
9 All eight DACs powered down.
VDD = 2.5 V to 5.5 V; RL = 2 kΩ to GND; CL = 200 pF to GND; all specifications TMIN to TMAX, unless otherwise noted.
Table 2. AC Characteristics1
Parameter3
Output Voltage Settling Time
AD5308
AD5318
AD5328
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Version2
Min Typ Max
Unit
68
79
8 10
0.7
12
0.5
0.5
1
3
200
−70
μs
μs
μs
V/μs
nV-sec
nV-sec
nV-sec
nV-sec
nV-sec
kHz
dB
Conditions/Comments
VREF = VDD = 5 V
1/4 scale to 3/4 scale change (0x40 to 0xC0)
1/4 scale to 3/4 scale change (0x100 To 0x300)
1/4 scale to 3/4 scale change (0x400 to 0xC00)
1 LSB change around major carry
VREF = 2 V ± 0.1 V p-p, unbuffered mode
VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Guaranteed by design and characterization; not production tested.
2 Temperature range (A, B version): –40°C to +125°C; typical at 25°C.
3 See the Terminology section.
Rev. F | Page 5 of 28
5 Page 
1.3
TA = 25°C
1.2
1.1 VREF = VDD
1.0
VREF = 2V, GAIN = +1,
BUFFERED
0.9
0.8
VREF = 2V, GAIN = +1, UNBUFFERED
0.7 VREF = VDD, GAIN = +1, UNBUFFERED
0.6
2.0 2.5 3.0 3.5 4.0 4.5
SUPPLY VOLTAGE (V)
Figure 16. Supply Current vs. Supply Voltage
5.0
1.0
0.9 TA = 25°C
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
2.0 2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 17. Power-Down Current vs. Supply Voltage
5.5
1.4
DECREASING
1.3
1.2
INCREASING
TA = 25°C
VDD = 5V
1.1
1.0
0.9
0.8
VDD = 3V
0.7
0.6
0
0.5 1.0 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0
VLOGIC (V)
Figure 18. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing
and Decreasing
AD5308/AD5318/AD5328
TA = 25°C
VDD = 5V
VREF = 5V
CH1
VOUTA
CH2
SCLK
CH1 1V, CH2 5V, TIME BASE = 1μs/DIV
Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
TA = 25°C
VDD = 5V
VREF = 2V
CH1
VDD
CH2
VOUTA
CH1 2.00V, CH2 200mV, TIME BASE = 200μs/DIV
Figure 20. Power-On Reset to 0 V
TA = 25°C
VDD = 5V
VREF = 2V
CH1
VOUTA
CH2
PD
CH1 500V, CH2 5.00mV, TIME BASE = 1μs/DIV
Figure 21. Exiting Power-Down to Midscale
Rev. F | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5328.PDF ] | |
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