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PDF AD5327 Data sheet ( Hoja de datos )
| Número de pieza | AD5327 | |
| Descripción | 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5327 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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2.5 V to 5.5 V, 400 μA, Quad Voltage Output,
8-/10-/12-Bit DACs in 16-Lead TSSOP
AD5307/AD5317/AD5327
FEATURES
GENERAL DESCRIPTION
AD5307: 4 buffered 8-bit DACs in 16-lead TSSOP
A version: ±1 LSB INL; B version: ±0.625 LSB INL
AD5317: 4 buffered 10-bit DACs in 16-lead TSSOP
A version: ±4 LSB INL; B version: ±2.5 LSB INL
AD5327: 4 buffered 12-bit DACs in 16-lead TSSOP
A version: ±16 LSB INL; B version: ±10 LSB INL
The AD5307/AD5317/AD53271 are quad 8-,10-,12-bit buffered
voltage-output DACs in 16-lead TSSOP that operate from single
2.5 V to 5.5 V supplies and consume 400 μA at 3 V. Their on-
chip output amplifiers allow the outputs to swing rail-to-rail with
a slew rate of 0.7 V/μs. The AD5307/AD5317/AD5327 utilize
Low power operation: 400 μA @ 3 V, 500 μA @ 5 V
versatile 3-wire serial interfaces that operate at clock rates up to
2.5 V to 5.5 V power supply
30 MHz; these parts are compatible with standard SPI, QSPI,
Guaranteed monotonic by design over all codes
Power down to 90 nA @ 3 V, 300 nA @ 5 V (LDAC pin)
Double-buffered input logic
Buffered/unbuffered reference input options
MICROWIRE, and DSP interface standards.
The references for the four DACs are derived from two reference
pins (one per DAC pair). These reference inputs can be configured
Output range: 0 V to VREF or 0 V to 2 VREF
Power-on reset to 0 V
as buffered or unbuffered inputs. Each part incorporates a power-
on reset circuit, ensuring that the DAC outputs power up to 0 V
Simultaneous update of outputs (LDAC pin)
and remain there until a valid write to the device takes place.
Asynchronous clear facility (CLR pin)
There is also an asynchronous active low CLR pin that clears all
Low power, SPI®-, QSPI™-, MICROWIRE™-, and DSP-
compatible 3-wire serial interface
SDO daisy-chaining option
On-chip rail-to-rail output buffer amplifiers
Temperature range of −40°C to +105°C
APPLICATIONS
Portable battery-powered instruments
DACs to 0 V. The outputs of all DACs can be updated simul-
taneously using the asynchronous LDAC input. Each part
contains a power-down feature that reduces the current
consumption of the device to 300 nA @ 5 V (90 nA @ 3 V). The
parts can also be used in daisy-chaining applications using the
SDO pin.
Digital gain and offset adjustment
All three parts are offered in the same pinout, allowing users to
Programmable voltage and current sources
select the amount of resolution appropriate for their application
Programmable attenuators
Industrial process control
without redesigning their circuit board.
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFAB
AD5307/AD5317/AD5327
LDAC
GAIN-SELECT
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
SCLK
SYNC
DIN
SDO
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
VOUTB
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
POWER-ON
RESET
BUFFER
VOUTD
POWER-DOWN
LOGIC
DCEN
LDAC CLR
Figure 1.
VREFCD
PD GND
1 Protected by U.S. Patent No. 5,969,657; other patents pending.
Rev. C
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD5307/AD5317/AD5327
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND. All specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2, 3
Output Voltage Settling Time
AD5307
AD5317
AD5327
Slew Rate
Major-Code Change Glitch Energy
Digital Feedthrough
SDO Feedthrough
Digital Crosstalk
Analog Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Versions1
Min Typ Max Unit Conditions/Comments
VREF = VDD = 5 V
68
μs 1/4 scale to 3/4 scale change (0x40 to 0xC0)
79
μs 1/4 scale to 3/4 scale change (0x100 to 0x300)
8 10 μs 1/4 scale to 3/4 scale change (0x400 to 0xC00)
0.7 V/μs
12 nV-s 1 LSB change around major carry
0.5 nV-s
4 nV-s Daisy-chain mode; SDO load is 10 pF
0.5 nV-s
1 nV-s
3 nV-s
200 kHz VREF = 2 V ± 0.1 V p-p; unbuffered mode
−70 dB VREF = 2.5 V ± 0.1 V p-p; frequency = 10 kHz
1 Temperature range (A, B versions): −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization; not production tested.
3 See the Terminology section.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V; all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2,
3
A, B Versions
Limit at TMIN, TMAX
Unit Conditions/Comments
t1
t2
t3
t4
t5
t6
t7
t8
t9
t10
t11
t12
t134, 5
t14
t15
t16
33
13
13
13
5
4.5
5
50
20
20
20
0
20
25
5
8
0
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns max
ns min
ns min
ns min
SCLK cycle time
SCLK high time
SCLK low time
SYNC to SCLK falling edge set-up time
Data set-up time
Data hold time
SCLK falling edge to SYNC rising edge
Minimum SYNC high time
LDAC pulse width
SCLK falling edge to LDAC rising edge
CLR pulse width
SCLK falling edge to LDAC falling edge
SCLK rising edge to SDO valid (VDD = 3.6 V to 5.5 V)
SCLK rising edge to SDO valid (VDD = 2.5 V to 3.5 V)
SCLK falling edge to SYNC rising edge
SYNC rising edge to SCLK rising edge
SYNC rising edge to LDAC falling edge
1 Guaranteed by design and characterization; not production tested.
2 All input signals are specified with tR = tF = 5 ns (10% to 90% of VDD) and timed from a voltage level of (VIL + VIH)/2.
3 See Figure 3 and Figure 4.
4 This is measured with the load circuit of Figure 2. t13 determines maximum SCLK frequency in daisy-chain mode.
5 Daisy-chain mode only.
Rev. C | Page 5 of 28
5 Page 
600
+25°C
500
–40°C
400
+105°C
300
200
100
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 18. Supply Current vs. Supply Voltage
5.5
0.5
0.4
0.3
–40°C
0.2 +25°C
0.1
+105°C
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 19. Power-Down Current vs. Supply Voltage
5.5
AD5307/AD5317/AD5327
CH1
TA = 25°C
VDD = 5V
VREF = 5V
VOUTA
SCLK
CH2
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
CH1
TA = 25°C
VDD = 5V
VREF = 2V
VDD
CH2
VOUTA
CH1 2.00V, CH2 200mV, TIME BASE = 200µs/DIV
Figure 22. Power-On Reset to 0 V
800
DECREASING
700
INCREASING
600
VDD = 5V
500
TA = 25°C
CH1
TA = 25°C
VDD = 5V
VREF = 2V
VOUTA
400
300
0
INCREASING
DECREASING
12
3
VDD = 3V
4
5
VLOGIC (V)
Figure 20. Supply Current vs. Logic Input Voltage for SCLK and DIN Increasing
and Decreasing
CH2
PD
CH1 500MV, CH2 5.00V, TIME BASE = 1µs/DIV
Figure 23. Exiting Power-Down to Midscale
Rev. C | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD5327.PDF ] | |
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