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PDF AD5325 Data sheet ( Hoja de datos )
| Número de pieza | AD5325 | |
| Descripción | 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5325 (archivo pdf) en la parte inferior de esta página. Total 24 Páginas | ||
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2.5 V to 5.5 V, 500 μA, 2-Wire Interface
Quad Voltage Output, 8-/10-/12-Bit DACs
AD5305/AD5315/AD5325
FEATURES
GENERAL DESCRIPTION
AD5305: 4 buffered 8-bit DACs in 10-lead MSOP
A version: ±1 LSB INL, B version: ±0.625 LSB INL
AD5315: 4 buffered 10-bit DACs in 10-lead MSOP
A version: ±4 LSB INL, B version: ±2.5 LSB INL
AD5325: 4 buffered 12-bit DACs in 10-lead MSOP
A version: ±16 LSB INL, B version: ±10 LSB INL
Low power operation: 500 μA @ 3 V, 600 μA @ 5 V
2-wire (I2C®-compatible) serial interface
2.5 V to 5.5 V power supply
Guaranteed monotonic by design over all codes
Power-down to 80 nA @ 3 V, 200 nA @ 5 V
Three power-down modes
The AD5305/AD5315/AD53251 are quad 8-, 10-, and 12-bit
buffered voltage output DACs in a 10-lead MSOP that operate
from a single 2.5 V to 5.5 V supply, consuming 500 μA at 3 V.
Their on-chip output amplifiers allow rail-to-rail output swing
with a slew rate of 0.7 V/μs. A 2-wire serial interface that
operates at clock rates up to 400 kHz is used. This interface is
SMBus compatible at VDD < 3.6 V. Multiple devices can be
placed on the same bus.
The references for the four DACs are derived from one
reference pin. The outputs of all DACs can be updated
simultaneously using the software LDAC function.
Double-buffered input logic
Output range: 0 V to VREF
Power-on reset to 0 V
Simultaneous update of outputs (LDAC function)
Software clear facility
Data readback facility
On-chip rail-to-rail output buffer amplifiers
The parts incorporate a power-on reset circuit, which ensures
that the DAC outputs power up to 0 V and remain there until a
valid write takes place to the device. There is also a software
clear function to reset all input and DAC registers to 0 V. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA @ 5 V (80 nA @ 3 V).
Temperature range: −40°C to +105°C
The low power consumption of these parts in normal operation
makes them ideally suited for portable battery-operated equip-
APPLICATIONS
Portable battery-powered instruments
ment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V,
reducing to 1 μW in power-down mode.
Digital gain and offset adjustment
Programmable voltage and current sources
Programmable attenuators
1 Protected by U.S. Patent No. 5,969,657 and 5,684,481.
Industrial process control
FUNCTIONAL BLOCK DIAGRAM
VDD REF IN
LDAC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC A
BUFFER
VOUTA
SCL
SDA
A0
INTERFACE
LOGIC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC B
BUFFER
INPUT
REGISTER
DAC
REGISTER
STRING
DAC C
BUFFER
VOUTB
VOUTC
INPUT
REGISTER
DAC
REGISTER
STRING
DAC D
BUFFER
VOUTD
POWER-ON
RESET
AD5305/AD5315/AD5325
POWER-DOWN
LOGIC
GND
Figure 1.
Rev. G
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
AD5305/AD5315/AD5325
AC CHARACTERISTICS
VDD = 2.5 V to 5.5 V, RL = 2 kΩ to GND, CL = 200 pF to GND, all specifications TMIN to TMAX, unless otherwise noted.
Table 2.
Parameter2, 3
Output Voltage Settling Time
AD5305
AD5315
AD5325
Slew Rate
Major-Code Transition Glitch Energy
Digital Feedthrough
Digital Crosstalk
DAC-to-DAC Crosstalk
Multiplying Bandwidth
Total Harmonic Distortion
A, B Version1
Min Typ Max Unit Conditions/Comments
VREF = VDD = 5 V
68
μs ¼ scale to ¾ scale change (0×40 to 0×C0)
79
μs ¼ scale to ¾ scale change (0×100 to 0×300)
8 10 μs ¼ scale to ¾ scale change (0×400 to 0×C00)
0.7 V/μs
12 nV-s 1 LSB change around major carry
1 nV-s
1 nV-s
3 nV-s
200 kHz VREF = 2 V ± 0.1 V p-p
−70 dB VREF = 2.5 V ± 0.1 V p-p, frequency = 10 kHz
1 Temperature range (A, B version): −40°C to +105°C; typical at +25°C.
2 Guaranteed by design and characterization, not production tested.
3 See the Terminology section.
TIMING CHARACTERISTICS
VDD = 2.5 V to 5.5 V, all specifications TMIN to TMAX, unless otherwise noted.
Table 3.
Parameter1, 2
fSCL
t1
t2
t3
t4
t5
t6 3
t7
t8
t9
t10
t11
CB4
Limit at TMIN, TMAX (A, B Version)
400
2.5
0.6
1.3
0.6
100
0.9
0
0.6
0.6
1.3
300
0
250
0
300
20 + 0.1 CB4
400
Unit
kHz max
μs min
μs min
μs min
μs min
ns min
μs max
μs min
μs min
μs min
μs min
ns max
ns min
ns max
ns min
ns max
ns min
pF max
Conditions/Comments
SCL clock frequency
SCL cycle time
tHIGH, SCL high time
tLOW, SCL low time
tHD,STA, start/repeated start condition hold time
tSU,DAT, data setup time
tHD,DAT, data hold time
tHD,DAT, data hold time
tSU,STA, setup time for repeated start
tSU,STO, stop condition setup time
tBUF, bus-free time between a stop and a start condition
tR, rise time of SCL and SDA when receiving
tR, rise time of SCL and SDA when receiving (CMOS compatible)
tF, fall time of SDA when transmitting
tF, fall time of SDA when receiving (CMOS compatible)
tF, fall time of SCL and SDA when receiving
tF, fall time of SCL and SDA when transmitting
Capacitive load for each bus line
1 See Figure 2.
2 Guaranteed by design and characterization; not production tested.
3 A master device must provide a hold time of at least 300 ns for the SDA signal (referred to VIH min of the SCL signal) in order to bridge the undefined region of SCL’s
falling edge.
4 CB is the total capacitance of one bus line in pF. tR and tF measured between 0.3 VDD and 0.7 VDD.
Rev. G | Page 5 of 24
5 Page 
600
–40°C
500
+25°C
400
+105°C
300
200
100
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 16. Supply Current vs. Supply Voltage
0.5
5.5
0.4
0.3
–40°C
0.2
+25°C
0.1
+105°C
0
2.5 3.0 3.5 4.0 4.5 5.0
VDD (V)
Figure 17. Power-Down Current vs. Supply Voltage
5.5
750
TA = 25°C
VDD = 5V
650
DECREASING
INCREASING
550
VDD = 3V
450 0 1 2 3 4 5
VLOGIC (V)
Figure 18. Supply Current vs. Logic Input Voltage for SDA and SCL
Voltage Increasing and Decreasing
AD5305/AD5315/AD5325
CH1
TA = 25°C
VDD = 5V
VREF = 5V
VOUTA
SCL
CH2
CH1 1V, CH2 5V, TIME BASE = 1µs/DIV
Figure 19. Half-Scale Settling (1/4 to 3/4 Scale Code Change)
CH1
TA = 25°C
VDD = 5V
VREF = 2V
VDD
CH2
VOUTA
CH1 2V, CH2 200mV, TIME BASE = 200µs/DIV
Figure 20. Power-On Reset to 0 V
CH1
TA = 25°C
VDD = 5V
VREF = 2V
VOUTA
SCL
CH2
CH1 500mV, CH2 5V, TIME BASE = 1µs/DIV
Figure 21. Exiting Power-Down to Midscale
Rev. G | Page 11 of 24
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD5325.PDF ] | |
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