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PDF AD5320 Data sheet ( Hoja de datos )
| Número de pieza | AD5320 | |
| Descripción | +2.7 V to +5.5 V/ 140 uA/ Rail-to-Rail Output 12-Bit DAC in a SOT-23 | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a +2.7 V to +5.5 V, 140 A, Rail-to-Rail Output
12-Bit DAC in a SOT-23
AD5320*
FEATURES
Single 12-Bit DAC
6-Lead SOT-23 and 8-Lead SOIC Packages
Micropower Operation: 140 A @ 5 V
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.7 V to +5.5 V Power Supply
Guaranteed Monotonic by Design
Reference Derived from Power Supply
Power-On-Reset to Zero Volts
Three Power-Down Functions
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Output Buffer Amplifier, Rail-to-Rail Operation
SYNC Interrupt Facility
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
FUNCTIONAL BLOCK DIAGRAM
VDD GND
POWER-ON
RESET
AD5320
DAC
REGISTER
REF (+) REF (–)
12-BIT
DAC
OUTPUT
BUFFER
VOUT
INPUT
CONTROL
LOGIC
POWER-DOWN
CONTROL LOGIC
RESISTOR
NETWORK
SYNC SCLK DIN
GENERAL DESCRIPTION
The AD5320 is a single, 12-bit buffered voltage out DAC that
operates from a single +2.7 V to +5.5 V supply consuming
115 µA at 3 V. Its on-chip precision output amplifier allows
rail-to-rail output swing to be achieved. The AD5320 utilizes a
versatile three-wire serial interface that operates at clock rates up
to 30 MHz and is compatible with standard SPI™, QSPI™,
MICROWIRE™ and DSP interface standards.
The reference for AD5320 is derived from the power supply
inputs and thus gives the widest dynamic output range. The part
incorporates a power-on-reset circuit that ensures that the DAC
output powers up to zero volts and remains there until a valid
write takes place to the device. The part contains a power-down
feature that reduces the current consumption of the device to
200 nA at 5 V and provides software selectable output loads
while in power-down mode. The part is put into power-down
mode over the serial interface.
The low power consumption of this part in normal operation
makes it ideally suited to portable battery operated equipment.
The power consumption is 0.7 mW at 5 V reducing to 1 µW in
power-down mode.
The AD5320 is one of a family of pin-compatible DACs. The
AD5300 is the 8-bit version and the AD5310 is the 10-bit
version. The AD5300/AD5310/AD5320 are available in 6-lead
SOT-23 packages and 8-lead µSOIC packages.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
*Patent pending; protected by U.S. Patent No. 5684481.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
PRODUCT HIGHLIGHTS
1. Available in 6-lead SOT-23 and 8-lead µSOIC packages.
2. Low power, single supply operation. This part operates from
a single +2.7 V to +5.5 V supply and typically consumes
0.35 mW at 3 V and 0.7 mW at 5 V, making it ideal for
battery powered applications.
3. The on-chip output buffer amplifier allows the output of the
DAC to swing rail-to-rail with a slew rate of 1 V/µs.
4. Reference derived from the power supply.
5. High speed serial interface with clock speeds up to 30 MHz.
Designed for very low power consumption. The interface
only powers up during a write cycle.
6. Power-down capability. When powered down, the DAC
typically consumes 50 nA at 3 V and 200 nA at 5 V.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
AD5320
TERMINOLOGY
Relative Accuracy
For the DAC, relative accuracy or Integral Nonlinearity (INL)
is a measure of the maximum deviation, in LSBs, from a straight
line passing through the endpoints of the DAC transfer func-
tion. A typical INL vs. code plot can be seen in Figure 2.
Differential Nonlinearity
Differential Nonlinearity (DNL) is the difference between the
measured change and the ideal 1 LSB change between any two
adjacent codes. A specified differential nonlinearity of ± 1 LSB
maximum ensures monotonicity. This DAC is guaranteed
monotonic by design. A typical DNL vs. code plot can be seen
in Figure 3.
Zero-Code Error
Zero-code error is a measure of the output error when zero code
(000 Hex) is loaded to the DAC register. Ideally the output
should be 0 V. The zero-code error is always positive in the
AD5320 because the output of the DAC cannot go below 0 V.
It is due to a combination of the offset errors in the DAC and
output amplifier. Zero-code error is expressed in mV. A plot of
zero-code error vs. temperature can be seen in Figure 6.
Full-Scale Error
Full-scale error is a measure of the output error when full-scale
code (FFF Hex) is loaded to the DAC register. Ideally the
output should be VDD – 1 LSB. Full-scale error is expressed in
percent of full-scale range. A plot of full-scale error vs. tempera-
ture can be seen in Figure 6.
Gain Error
This is a measure of the span error of the DAC. It is the devia-
tion in slope of the DAC transfer characteristic from ideal
expressed as a percent of the full-scale range.
Total Unadjusted Error
Total Unadjusted Error (TUE) is a measure of the output error
taking all the various errors into account. A typical TUE vs.
code plot can be seen in Figure 4.
Zero-Code Error Drift
This is a measure of the change in zero-code error with a
change in temperature. It is expressed in µV/°C.
Gain Error Drift
This is a measure of the change in gain error with changes in
temperature. It is expressed in (ppm of full-scale range)/°C.
Digital-to-Analog Glitch Impulse
Digital-to-analog glitch impulse is the impulse injected into the
analog output when the input code in the DAC register changes
state. It is normally specified as the area of the glitch in nV secs
and is measured when the digital input code is changed by
1 LSB at the major carry transition (7FF Hex to 800 Hex). See
Figure 19.
Digital Feedthrough
Digital feedthrough is a measure of the impulse injected into the
analog output of the DAC from the digital inputs of the DAC
but is measured when the DAC output is not updated. It is
specified in nV secs and measured with a full-scale code
change on the data bus, i.e., from all 0s to all 1s and vice versa.
REV. B
–5–
5 Page 
AD5320
Bipolar Operation Using the AD5320
The AD5320 has been designed for single-supply operation but
a bipolar output range is also possible using the circuit in Figure
30. The circuit below will give an output voltage range of ± 5 V.
Rail-to-rail operation at the amplifier output is achievable using
an AD820 or an OP295 as the output amplifier.
The output voltage for any input code can be calculated as
follows:
VO
=
V DD
×
D
4096
×
R1+ R2
R1
–V DD
×
R2
R1
where D represents the input code in decimal (0–4095).
With VDD = 5 V, R1 = R2 = 10 kΩ:
VO
=
10 × D
4096
– 5V
This is an output voltage range of ± 5 V with 000 Hex corre-
sponding to a –5 V output and FFF Hex corresponding to a
+5 V output.
+5V R1 = 10k⍀
10F 0.1F
VDD
VOUT
AD5320
R2 = 10k⍀
+5V
AD820/
OP295
–5V
؎5V
THREE-WIRE
SERIAL
INTERFACE
Figure 30. Bipolar Operation with the AD5320
Using AD5320 with an Opto-Isolated Interface
In process-control applications in industrial environments it is
often necessary to use an opto-isolated interface to protect and
isolate the controlling circuitry from any hazardous common-
mode voltages that may occur in the area where the DAC is
functioning. Opto-isolators provide isolation in excess of 3 kV.
Because the AD5320 uses a three-wire serial logic interface, it
requires only three opto-isolators to provide the required isola-
tion (see Figure 31). The power supply to the part also needs to
be isolated. This is done by using a transformer. On the DAC
side of the transformer, a +5 V regulator provides the +5 V
supply required for the AD5320.
POWER
SCLK
SYNC
DATA
+5V
REGULATOR
10F 0.1F
VDD
10k⍀
SCLK
VDD
VDD
10k⍀
AD5320
SYNC
VOUT
VDD
10k⍀
DIN
GND
Figure 31. AD5320 with An Opto-Isolated Interface
Power Supply Bypassing and Grounding
When accuracy is important in a circuit it is helpful to carefully
consider the power supply and ground return layout on the
board. The printed circuit board containing the AD5320 should
have separate analog and digital sections, each having its own
area of the board. If the AD5320 is in a system where other
devices require an AGND to DGND connection, the connec-
tion should be made at one point only. This ground point
should be as close as possible to the AD5320.
The power supply to the AD5320 should be bypassed with
10 µF and 0.1 µF capacitors. The capacitors should be physi-
cally as close as possible to the device with the 0.1 µF capacitor
ideally right up against the device. The 10 µF capacitors are the
tantalum bead type. It is important that the 0.1 µF capacitor has
low Effective Series Resistance (ESR) and Effective Series In-
ductance (ESI), e.g., common ceramic types of capacitors. This
0.1 µF capacitor provides a low impedance path to ground for
high frequencies caused by transient currents due to internal
logic switching.
The power supply line itself should have as large a trace as pos-
sible to provide a low impedance path and reduce glitch effects
on the supply line. Clocks and other fast switching digital signals
should be shielded from other parts of the board by digital
ground. Avoid crossover of digital and analog signals if possible.
When traces cross on opposite sides of the board, ensure that
they run at right angles to each other to reduce feedthrough
effects through the board. The best board layout technique is
the microstrip technique where the component side of the board
is dedicated to the ground plane only and the signal traces are
placed on the solder side. However, this is not always possible
with a two-layer board.
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD5320.PDF ] | |
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