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PDF AD5313 Data sheet ( Hoja de datos )
| Número de pieza | AD5313 | |
| Descripción | +2.5 V to +5.5 V/ 230 uA/ Dual Rail-to-Rail Voltage Output 8-/10-/12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD5313 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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a +2.5 V to +5.5 V, 230 A, Dual Rail-to-Rail
Voltage Output 8-/10-/12-Bit DACs
AD5303/AD5313/AD5323*
FEATURES
AD5303: Two Buffered 8-Bit DACs in One Package
AD5313: Two Buffered 10-Bit DACs in One Package
AD5323: Two Buffered 12-Bit DACs in One Package
16-Lead TSSOP Package
Micropower Operation: 300 A @ 5 V (Including
Reference Current)
Power-Down to 200 nA @ 5 V, 50 nA @ 3 V
+2.5 V to +5.5 V Power Supply
Double-Buffered Input Logic
Guaranteed Monotonic By Design Over All Codes
Buffered/Unbuffered Reference Input Options
Output Range: 0–VREF or 0–2 VREF
Power-On-Reset to Zero Volts
SDO Daisy-Chaining Option
Simultaneous Update of DAC Outputs via LDAC Pin
Asynchronous CLR Facility
Low Power Serial Interface with Schmitt-Triggered
Inputs
On-Chip Rail-to-Rail Output Buffer Amplifiers
APPLICATIONS
Portable Battery Powered Instruments
Digital Gain and Offset Adjustment
Programmable Voltage and Current Sources
Programmable Attenuators
GENERAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual 8-, 10- and 12-bit
buffered voltage output DACs in a 16-lead TSSOP package that
operate from a single +2.5 V to +5.5 V supply consuming 230 µA
at 3 V. Their on-chip output amplifiers allow the outputs to
swing rail-to-rail with a slew rate of 0.7 V/µs. The AD5303/
AD5313/AD5323 utilize a versatile 3-wire serial interface that
operates at clock rates up to 30 MHz and is compatible with
standard SPI™, QSPI, MICROWIRE™ and DSP interface
standards.
The references for the two DACs are derived from two reference
pins (one per DAC). These reference inputs may be configured
as buffered or unbuffered inputs. The parts incorporate a power-
on-reset circuit that ensures that the DAC outputs power-up to
0 V and remain there until a valid write to the device takes place.
There is also an asynchronous active low CLR pin that clears
both DACs to 0 V. The outputs of both DACs may be updated
simultaneously using the asynchronous LDAC input. The
parts contain a power-down feature that reduces the current
consumption of the devices to 200 nA at 5 V (50 nA at 3 V) and
provides software-selectable output loads while in power-down
mode. The parts may also be used in daisy-chaining applications
using the SDO pin.
The low power consumption of these parts in normal operation
make them ideally suited to portable battery operated equip-
ment. The power consumption is 1.5 mW at 5 V, 0.7 mW at
3 V, reducing to 1 µW in power-down mode.
FUNCTIONAL BLOCK DIAGRAM
VDD
BUF A
VREFA
SYNC
SCLK
DIN
POWER-ON
RESET
INPUT
REGISTER
INTERFACE
LOGIC
>
DAC
REGISTER
AD5303/AD5313/AD5323
STRING
DAC
BUFFER
POWER-DOWN
LOGIC
VOUTA
RESISTOR
NETWORK
INPUT
REGISTER
DAC
REGISTER
STRING
DAC
BUFFER
VOUTB
SDO
GAIN-SELECT
LOGIC
RESISTOR
NETWORK
DCEN LDAC CLR
PD
*Protected by U.S. Patent No. 5684481; other patents pending.
SPI is a trademark of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
BUF B
VREFB
GND
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
ABSOLUTE MAXIMUM RATINGS1, 2
(TA = +25°C unless otherwise noted)
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
Digital Input Voltage to GND . . . . . . . –0.3 V to VDD + 0.3 V
Digital Output Voltage to GND . . . . . –0.3 V to VDD + 0.3 V
Reference Input Voltage to GND . . . . –0.3 V to VDD + 0.3 V
VOUTA, VOUTB to GND . . . . . . . . . . . –0.3 V to VDD + 0.3 V
Operating Temperature Range
Industrial (B Version) . . . . . . . . . . . . . . . –40°C to +105°C
Storage Temperature Range . . . . . . . . . . . . –65°C to +150°C
Junction Temperature (TJ Max) . . . . . . . . . . . . . . . . . +150°C
16-Lead TSSOP Package
Power Dissipation . . . . . . . . . . . . . . . . . . (TJ Max – TA)/θJA
θJA Thermal Impedance . . . . . . . . . . . . . . . . . . . . 160°C/W
Lead Temperature, Soldering
Vapor Phase (60 sec) . . . . . . . . . . . . . . . . . . . . . .+215°C
Infrared (15 sec) . . . . . . . . . . . . . . . . . . . . . . . . . .+220°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only; functional operation of the
device at these or any other conditions above those listed in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2Transient currents of up to 100 mA will not cause SCR latch-up.
AD5303/AD5313/AD5323
PIN CONFIGURATION
CLR 1
16 SDO
LDAC 2
15 GND
AD5303/
VDD 3 AD5313/ 14 DIN
VREFB 4 AD5323 13 SCLK
TOP VIEW
VREFA 5 (Not to Scale) 12 SYNC
VOUTA 6
11 VOUTB
BUF A 7
10 PD
BUF B 8
9 DCEN
Model
AD5303BRU
AD5313BRU
AD5323BRU
Temperature Range
–40°C to +105°C
–40°C to +105°C
–40°C to +105°C
ORDERING GUIDE
Package Description
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Thin Shrink Small Outline Package (TSSOP)
Package Option
RU-16
RU-16
RU-16
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD5303/AD5313/AD5323 features proprietary ESD protection circuitry, perma-
nent damage may occur on devices subjected to high energy electrostatic discharges. Therefore,
proper ESD precautions are recommended to avoid performance degradation or loss of functionality.
WARNING!
ESD SENSITIVE DEVICE
REV. 0
–5–
5 Page 
AD5303/AD5313/AD5323
FUNCTIONAL DESCRIPTION
The AD5303/AD5313/AD5323 are dual resistor-string DACs
fabricated on a CMOS process with resolutions of 8, 10 and 12
bits respectively. They contain reference buffers, output buffer
amplifiers and are written to via a 3-wire serial interface. They
operate from single supplies of +2.5 V to +5.5 V and the output
buffer amplifiers provide rail-to-rail output swing with a slew
rate of 0.7 V/µs. Each DAC is provided with a separate refer-
ence input, which may be buffered to draw virtually no current
from the reference source, or unbuffered to give a reference
input range from GND to VDD. The devices have three pro-
grammable power-down modes, in which one or both DACs
may be turned off completely with a high-impedance output, or
the output may be pulled low by an on-chip resistor.
Digital-to-Analog Section
The architecture of one DAC channel consists of a reference
buffer and a resistor-string DAC followed by an output buffer
amplifier. The voltage at the VREF pin provides the reference
voltage for the DAC. Figure 27 shows a block diagram of the
DAC architecture. Since the input coding to the DAC is straight
binary, the ideal output voltage is given by:
where
VOUT
=VREF × D
2N
D = decimal equivalent of the binary code, which is loaded to
the DAC register;
0–255 for AD5303 (8 Bits)
0–1023 for AD5313 (10 Bits)
0–4095 for AD5323 (12 Bits)
N = DAC resolution
VREFA
REFERENCE
BUFFER
BUF A
INPUT
REGISTER
DAC
REGISTER
RESISTOR
STRING
VOUTA
OUTPUT BUFFER
AMPLIFIER
Figure 27. Single DAC Channel Architecture
Resistor String
The resistor string section is shown in Figure 28. It is simply a
string of resistors, each of value R. The digital code loaded to
the DAC register determines at what node on the string the
voltage is tapped off to be fed into the output amplifier. The
voltage is tapped off by closing one of the switches connecting
the string to the amplifier. Because it is a string of resistors, it is
guaranteed monotonic.
R
R
R
TO OUTPUT
AMPLIFIER
R
R
Figure 28. Resistor String
DAC Reference Inputs
There is a reference input pin for each of the two DACs. The
reference inputs are buffered but can also be configured as un-
buffered. The advantage with the buffered input is the high
impedance it presents to the voltage source driving it. However,
if the unbuffered mode is used, the user can have a reference
voltage as low as GND and as high as VDD since there is no restric-
tion due to headroom and footroom of the reference amplifier.
If there is a buffered reference in the circuit (e.g., REF192), there
is no need to use the on-chip buffers of the AD5303/AD5313/
AD5323. In unbuffered mode the input impedance is still large
at typically 180 kΩ per reference input for 0–VREF mode and
90 kΩ for 0–2 VREF mode.
The buffered/unbuffered option is controlled by the BUF A and
BUF B pins. If the BUF pin is tied high, the reference input is
buffered, if tied low, it is unbuffered.
Output Amplifier
The output buffer amplifier is capable of generating output
voltages to within 1 mV of either rail which gives an output
range of 0.001 V to VDD – 0.001 V when the reference is VDD. It
is capable of driving a load of 2 kΩ in parallel with 500 pF to
GND and VDD. The source and sink capabilities of the output
amplifier can be seen in Figure 15.
The slew rate is 0.7 V/µs with a half-scale settling time to
± 0.5 LSB (at 8 bits) of 6 µs.
POWER-ON RESET
The AD5303/AD5313/AD5323 are provided with a power-on
reset function, so that they power up in a defined state. The
power-on state is:
– Normal operation.
– 0–VREF output range.
– Output voltage set to 0 V.
Both input and DAC registers are filled with zeros and remain
so until a valid write sequence is made to the device. This is
particularly useful in applications where it is important to know
the state of the DAC outputs while the device is powering up.
Clear Function (CLR)
The CLR pin is an active low input which, when pulled low,
loads all zeros to both input registers and both DAC registers.
This enables both analog outputs to be cleared to 0 V.
REV. 0
–11–
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD5313.PDF ] | |
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