PDF AD53040 Data sheet ( Hoja de datos )

Número de pieza	AD53040
Descripción	Ultrahigh Speed Pin Driver
Fabricantes	Analog Devices
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No Preview Available ! a FEATURES 500 MHz Driver Operation Driver Inhibit Function 100 ps Edge Matching Guaranteed Industry Specifications 50 ⍀ Output Impedance >1.5 V/ns Slew Rate Variable Output Voltages for ECL, TTL and CMOS High Speed Differential Inputs for Maximum Flexibility Ultrasmall 20-Lead SOP Package with Built-In Heat Sink APPLICATIONS Automatic Test Equipment Semiconductor Test Systems Board Test Systems Instrumentation and Characterization Equipment Ultrahigh Speed Pin Driver with Inhibit Mode AD53040 FUNCTIONAL BLOCK DIAGRAM VCC VCC VEE VEE VH DATA DATA INH INH VL DRIVER AD53040 50⍀ 1.0␮A/K 39nF 39nF VHDCPL VOUT VLDCPL TVCC THERM GND GND GND GND GND PRODUCT DESCRIPTION The AD53040 is a complete high speed pin driver designed for use in digital or mixed-signal test systems. Combining a high speed monolithic process with a unique surface mount package, this product attains superb electrical performance while preserv- ing optimum packaging densities and long-term reliability in an ultrasmall 20-lead, SOP package with built-in heat sink. Featuring unity gain programmable output levels of –3 V to +8 V, with output swing capability of less than 100 mV to 9 V, the AD53040 is designed to stimulate ECL, TTL and CMOS logic families. The 500 MHz data rate capacity and matched output impedance allows for real-time stimulation of these digital logic families. To test I/O devices, the pin driver can be switched into a high impedance state (Inhibit Mode), electri- cally removing the driver from the path. The pin driver leakage current inhibit is typically 100 nA and output charge transfer entering inhibit is typically less than 20 pC. The AD53040 transition from HI/LO or to inhibit is controlled through the data and inhibit inputs. The input circuitry uses high speed differential inputs with a common-mode range of ± 3 V. This allows for direct interface to precision differential ECL timing or the simplicity of stimulating the pin driver from a single ended TTL or CMOS logic source. The analog logic HI/LO inputs are equally easy to interface. Typically requiring 10 µA of bias current, the AD53040 can be directly coupled to the output of a digital-to-analog converter. The AD53040 is available in a 20-lead, SOP package with a built-in heat sink and is specified to operate over the ambient commercial temperature range of –25°C to +85°C. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page AD53040 APPLICATION INFORMATION Power Supply Distribution, Bypassing and Sequencing The AD53040 draws substantial transient currents from its power supplies when switching between states and careful design of the power distribution and bypassing is key to obtaining speci- fied performance. Supplies should be distributed using broad, low inductance traces or (preferably) planes in a multilayered board with a dedicated ground-plane layer. All of the device’s power supply pins should be used to minimize the internal in- ductance presented by the part’s bond wires. Each supply must be bypassed to ground with at least one 0.1 µF capacitor; chip- style capacitors are preferable as they minimize inductance. One or more 10 µF (or greater) Tantalum capacitors per board are also advisable to provide additional local energy storage. The AD53040’s current-limit circuitry also requires external bypass capacitors. Figure 1 shows a simplified schematic of the positive current-limit circuit. Excessive collector current in out- put transistor Q49 creates a voltage drop across the 10 Ω resis- tor, which turns on PNP transistor Q48. Q48 diverts the rising- edge slew current, shutting down the current mirror and remov- ing the output stage’s base drive. The VHDCPL pin should be bypassed to the positive supply with a 0.039 µF capacitor, while the VLDCPL pin (not shown) requires a similar capacitor to the negative supply- these capacitors ensure that the AD53040 doesn’t current limit during normal output transitions up the its full 9 V rated step size. Both capacitors must have minimum- length connections to the AD53040. Here again, chip capacitors are ideal. VPOS 10⍀؎10% Q48 VHDCPL RISING-EDGE SLEW CONTROL CURRENT LEVEL-SHIFTED LOGIC DRIVE VNEG Q49 VH Several points about the current-limit circuitry should be noted. First, the limiting currents are not tightly controlled, as they are functions of both absolute transistor VBES and junction tem- perature; higher dc output current is available at lower junction temperatures. Second, it is essential to connect the VHDCPL capacitor to the positive supply (and the VLDCPL capacitor to the negative supply)—failure to do so causes considerable ther- mal stress in the current-limiting resistor(s) during normal sup- ply sequencing and may ultimately cause them to fail, rendering the part nonfunctional. Finally, the AD53040 may appear to function normally for small output steps (less than 3 V or so) if one or both of these capacitors is absent, but it will exhibit excessive rise or fall times for steps of larger amplitude. The AD53040 does not require special power-supply sequencing. However, good design practice dictates that digital and analog control signals not be applied to the part before the supplies are stable. Violating this guideline will not normally destroy the part, but the active inputs can draw considerable current until the main supplies are applied. Digital Input Range Restrictions Total range amongst all digital signals (DATA, DATA, INH, and INH) has to be less than or equal to 2 V to meet specified timing. The device will function above 2 V with reduced perfor- mance up to the absolute maximum limit. This performance degradation might not be noticed in all modes of operation. Of all the six possible transitions (VH v VL, VL v VH, VH v INH, INH v VH, VL v INH and INH v VL), there may be only one that would show a degradation, usually in delay time. Taken to the extreme, the driver may fail to achieve a proper output volt- age, output impedance or may fail to fully inhibit. An example of a scenario that would not work for the AD53040 is if the part is driven using 5 V single-ended CMOS. One pin of each differential input would be tied to a +2.5 V reference level and the logic voltages would be applied to the other. This would meet the Absolute Maximum Rating of ± 3 V because the max differential is ± 2.5 V. It is however possible, for example for 0.0 V to be applied to the INH input and +5 V to be applied to the DATA input. This 5 V difference far exceeds the 2.0 V limitation given above. Even using 3 V CMOS or TTL the difference between logic high and logic low is greater than or equal to 3 V which will not properly work. The only solution is to use resistive dividers or equivalent to reduce the voltage levels. OUT Q50 Figure 1. Simplified Schematic of the AD53040 Output Stage and Positive Current Limit Circuitry 5.12V 550mV /DIV REV. B –380mV 66.25ns 500ps/DIV 71.25ns Figure 2. 5 V Output Swing –5– 5 Page

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