PDF AD5304 Data sheet ( Hoja de datos )

Número de pieza	AD5304
Descripción	2.5 V to 5.5 V/ 500 uA/ Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC
Fabricantes	Analog Devices
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No Preview Available ! a 2.5 V to 5.5 V, 500 ␮A, Quad Voltage Output 8-/10-/12-Bit DACs in 10-Lead microSOIC AD5304/AD5314/AD5324* FEATURES AD5304 Four Buffered 8-Bit DACs in 10-Lead microSOIC AD5314 Four Buffered 10-Bit DACs in 10-Lead microSOIC AD5324 Four Buffered 12-Bit DACs in 10-Lead microSOIC Low Power Operation: 500 ␮A @ 3 V, 600 ␮A @ 5 V 2.5 V to 5.5 V Power Supply Guaranteed Monotonic By Design Over All Codes Power-Down to 80 nA @ 3 V, 200 nA @ 5 V Double-Buffered Input Logic Output Range: 0–VREF Power-On-Reset to Zero Volts Simultaneous Update of Outputs (LDAC Function) Low Power, SPI™, QSPI™, MICROWIRE™, and DSP-Compatible 3-Wire Serial Interface On-Chip Rail-to-Rail Output Buffer Ampliﬁers Temperature Range –40؇C to +105؇C APPLICATIONS Portable Battery-Powered Instruments Digital Gain and Offset Adjustment Programmable Voltage and Current Sources Programmable Attenuators Industrial Process Control GENERAL DESCRIPTION The AD5304/AD5314/AD5324 are quad 8-, 10- and 12-bit buffered voltage output DACs in a 10-lead microSOIC package that operate from a single 2.5 V to 5.5 V supply consuming 500 µA at 3 V. Their on-chip output ampliﬁers allow rail-to- rail output swing to be achieved with a slew rate of 0.7 V/µs. A 3-wire serial interface is used which operates at clock rates up to 30 MHz and is compatible with standard SPI, QSPI, MICROWIRE and DSP interface standards. The references for the four DACs are derived from one reference pin. The outputs of all DACs may be updated simultaneously using the software LDAC function. The parts incorporate a power-on-reset circuit that ensures that the DAC outputs power up to zero volts and remain there until a valid write takes place to the device. The parts contain a power-down feature that reduces the current consumption of the device to 200 nA @ 5 V (80 nA @ 3 V). The low power consumption of these parts in normal operation makes them ideally suited to portable battery-operated equipment. The power consumption is 3 mW at 5 V, 1.5 mW at 3 V, reducing to 1 µW in power-down mode. FUNCTIONAL BLOCK DIAGRAM LDAC VDD REFIN INPUT REGISTER DAC REGISTER STRING BUFFER DAC A VOUTA SCLK SYNC DIN INTERFACE LOGIC INPUT REGISTER DAC REGISTER STRING DAC B BUFFER INPUT REGISTER DAC REGISTER STRING DAC C BUFFER VOUTB VOUTC INPUT REGISTER DAC REGISTER STRING DAC D BUFFER VOUTD POWER-DOWN POWER-ON RESET AD5304/AD5314/AD5324 LOGIC GND Protected by U.S. Patent No. 5,969,657; other patents pending. SPI and QSPI are trademarks of Motorola, Inc. MICROWIRE is a trademark of National Semiconductor Corporation. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page AD5304/AD5314/AD5324 TERMINOLOGY RELATIVE ACCURACY For the DAC, relative accuracy or integral nonlinearity (INL) is a measure of the maximum deviation, in LSBs, from a straight line passing through the endpoints of the DAC transfer function. Typical INL versus Code plots can be seen in Figures 4, 5, and 6. DIFFERENTIAL NONLINEARITY Differential Nonlinearity (DNL) is the difference between the measured change and the ideal 1 LSB change between any two adjacent codes. A speciﬁed differential nonlinearity of ± 1 LSB maximum ensures monotonicity. This DAC is guaranteed mono- tonic by design. Typical DNL versus Code plots can be seen in Figures 7, 8, and 9. DIGITAL CROSSTALK This is the glitch impulse transferred to the output of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) in the input register of another DAC. It is expressed in nV-secs. DAC-TO-DAC CROSSTALK This is the glitch impulse transferred to the output of one DAC due to a digital code change and subsequent output change of another DAC. This includes both digital and analog crosstalk. It is measured by loading one of the DACs with a full-scale code change (all 0s to all 1s and vice versa) with the LDAC bit set low and monitoring the output of another DAC. The energy of the glitch is expressed in nV-secs. OFFSET ERROR This is a measure of the offset error of the DAC and the output ampliﬁer. It is expressed as a percentage of the full-scale range. GAIN ERROR This is a measure of the span error of the DAC. It is the devia- tion in slope of the actual DAC transfer characteristic from the ideal expressed as a percentage of the full-scale range. OFFSET ERROR DRIFT This is a measure of the change in offset error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. GAIN ERROR DRIFT This is a measure of the change in gain error with changes in temperature. It is expressed in (ppm of full-scale range)/°C. POWER-SUPPLY REJECTION RATIO (PSRR) This indicates how the output of the DAC is affected by changes in the supply voltage. PSRR is the ratio of the change in VOUT to a change in VDD for full-scale output of the DAC. It is measured in dBs. VREF is held at 2 V and VDD is varied ± 10%. DC CROSSTALK This is the dc change in the output level of one DAC at midscale in response to a full-scale code change (all 0s to all 1s and vice versa) and output change of another DAC. It is expressed in µV. REFERENCE FEEDTHROUGH This is the ratio of the amplitude of the signal at the DAC output to the reference input when the DAC output is not being updated. It is expressed in dBs. MULTIPLYING BANDWIDTH The ampliﬁers within the DAC have a ﬁnite bandwidth. The multiplying bandwidth is a measure of this. A sine wave on the reference (with full-scale code loaded to the DAC) appears on the output. The multiplying bandwidth is the frequency at which the output amplitude falls to 3 dB below the input. TOTAL HARMONIC DISTORTION This is the difference between an ideal sine wave and its attenuated version using the DAC. The sine wave is used as the reference for the DAC and the THD is a measure of the harmonics present on the DAC output. It is measured in dBs. OUTPUT VOLTAGE IDEAL GAIN ERROR PLUS OFFSET ERROR ACTUAL NEGATIVE OFFSET ERROR DAC CODE AMPLIFIER FOOTROOM (1mV) NEGATIVE OFFSET ERROR DEADBAND CODES Figure 2. Transfer Function with Negative Offset MAJOR-CODE TRANSITION GLITCH ENERGY Major-code transition glitch energy is the energy of the impulse injected into the analog output when the code in the DAC register changes state. It is normally speciﬁed as the area of the glitch in nV-secs and is measured when the digital code is changed by 1 LSB at the major carry transition (011 . . . 11 to 100 . . . 00 or 100 . . . 00 to 011 . . . 11). DIGITAL FEEDTHROUGH Digital feedthrough is a measure of the impulse injected into the analog output of the DAC from the digital input pins of the device when the DAC output is not being written to (SYNC held high). It is speciﬁed in nV-secs and is measured with a worst-case change on the digital input pins, e.g., from all 0s to all 1s or vice versa. REV. B –5– OUTPUT VOLTAGE ACTUAL GAIN ERROR PLUS OFFSET ERROR IDEAL POSITIVE OFFSET DAC CODE Figure 3. Transfer Function with Positive Offset 5 Page AD5304/AD5314/AD5324 When the PD bit is set to 1, all DACs work normally with a typical power consumption of 600 µA at 5 V (500 µA at 3 V). However, in power-down mode, the supply current falls to 200 nA at 5 V (80 nA at 3 V) when all DACs are powered down. Not only does the supply current drop, but the output stage is also internally switched from the output of the ampliﬁer making it open-circuit. This has the advantage that the output is three- stated while the part is in power-down mode, and provides a deﬁned input condition for whatever is connected to the output of the DAC ampliﬁer. The output stage is illustrated in Figure 32. The bias generator, the output ampliﬁer, the resistor string, and all other associated linear circuitry are all shut down when the power-down mode is activated. However, the contents of the registers are unaffected when in power-down. The time to exit power-down is typically 2.5 µs for VDD = 5 V and 5 µs when VDD = 3 V. This is the time from the falling edge of the sixteenth SCLK pulse to when the output voltage deviates from its power- down voltage. See Figure 21 for a plot. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface Figure 34 shows a serial interface between the AD5304/AD5314/ AD5324 and the 68HC11/68L11 microcontroller. SCK of the 68HC11/68L11 drives the SCLK of the AD5304/AD5314/ AD5324, while the MOSI output drives the serial data line (DIN) of the DAC. The SYNC signal is derived from a port line (PC7). The setup conditions for correct operation of this interface are as follows: the 68HC11/68L11 should be conﬁgured so that its CPOL bit is a 0 and its CPHA bit is a 1. When data is being transmitted to the DAC, the SYNC line is taken low (PC7). When the 68HC11/68L11 is conﬁgured as above, data appearing on the MOSI output is valid on the falling edge of SCK. Serial data from the 68HC11/68L11 is transmitted in 8-bit bytes with only eight falling clock edges occurring in the transmit cycle. Data is transmitted MSB ﬁrst. In order to load data to the AD5304/ AD5314/AD5324, PC7 is left low after the ﬁrst eight bits are transferred, a second serial write operation is performed to the DAC, and PC7 is taken high at the end of this procedure. RESISTOR STRING DAC AMPLIFIER VOUT POWER-DOWN CIRCUITRY Figure 32. Output Stage During Power-Down MICROPROCESSOR INTERFACING AD5304/AD5314/AD5324 to ADSP-2101/ADSP-2103 Interface Figure 33 shows a serial interface between the AD5304/AD5314/ AD5324 and the ADSP-2101/ADSP-2103. The ADSP-2101/ ADSP-2103 should be set up to operate in the SPORT Transmit Alternate Framing Mode. The ADSP-2101/ADSP-2103 SPORT is programmed through the SPORT control register and should be conﬁgured as follows: Internal Clock Operation, Active-Low Framing, 16-Bit Word Length. Transmission is initiated by writing a word to the Tx register after the SPORT has been enabled. The data is clocked out on each rising edge of the DSP’s serial clock and clocked into the AD5304/AD5314/AD5324 on the falling edge of the DAC’s SCLK. ADSP-2101/ ADSP-2103 TFS DT SCLK AD5304/ AD5314/ AD5324* SYNC DIN SCLK ADDITIONAL PINS OMITTED FOR CLARITY. Figure 33. AD5304/AD5314/AD5324 to ADSP-2101/ ADSP-2103 Interface 68HC11/68L11 PC7 SCK MOSI AD5304/ AD5314/ AD5324* SYNC SCLK DIN ADDITIONAL PINS OMITTED FOR CLARITY. Figure 34. AD5304/AD5314/AD5324 to 68HC11/68L11 Interface AD5304/AD5314/AD5324 to 80C51/80L51 Interface Figure 35 shows a serial interface between the AD5304/AD5314/ AD5324 and the 80C51/80L51 microcontroller. The setup for the interface is as follows: TxD of the 80C51/80L51 drives SCLK of the AD5304/AD5314/AD5324, while RxD drives the serial data line of the part. The SYNC signal is again derived from a bit-programmable pin on the port. In this case port line P3.3 is used. When data is to be transmitted to the AD5304/AD5314/ AD5324, P3.3 is taken low. The 80C51/80L51 transmits data only in 8-bit bytes; thus only eight falling clock edges occur in the transmit cycle. To load data to the DAC, P3.3 is left low after the ﬁrst eight bits are transmitted, and a second write cycle is initiated to transmit the second byte of data. P3.3 is taken high following the completion of this cycle. The 80C51/80L51 outputs the serial data in a format which has the LSB ﬁrst. The AD5304/ AD5314/AD5324 requires its data with the MSB as the ﬁrst bit received. The 80C51/80L51 transmit routine should take this into account. 80C51/80L51 P3.3 TxD RxD AD5304/ AD5314/ AD5324* SYNC SCLK DIN *ADDITIONAL PINS OMITTED FOR CLARITY. Figure 35. AD5304/AD5314/AD5324 to 80C51/80L51 Interface REV. B –11– 11 Page

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