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PDF AD5245 Data sheet ( Hoja de datos )
| Número de pieza | AD5245 | |
| Descripción | 256-Position I2C Compatible Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
256-position
End-to-end resistance 5 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Compact SOT-23-8 (2.9 mm × 3 mm) package
Fast settling time: tS = 5 µs typ on power-up
Full read/write of wiper register
Power-on preset to midscale
Extra package address decode pin AD0
Computer software replaces µC in factory programming
applications
Single supply: 2.7 V to 5.5 V
Low temperature coefficient 45 ppm/°C
Low power: IDD = 8 µA
Wide operating temperature: –40°C to +125°C
Evaluation board available
APPLICATIONS
Mechanical potentiometer replacement in new designs
LCD panel VCOM adjustment
LCD panel brightness and contrast control
Transducer adjustment of pressure, temperature, position,
chemical, and optical sensors
RF amplifier biasing
Automotive electronics adjustment
Gain control and offset adjustment
GENERAL DESCRIPTION
The AD5245 provides a compact 2.9 mm × 3 mm packaged
solution for 256-position adjustment applications. These
devices perform the same electronic adjustment function as
mechanical potentiometers or variable resistors, with enhanced
resolution, solid-state reliability, and superior low temperature
coefficient performance.
The wiper settings are controllable through an I2C-compatible
digital interface, which can also be used to read back the wiper
register content. AD0 can be used to place up to two devices on
the same bus. Command bits are available to reset the wiper
position to midscale or to shut down the device into a state of
zero power consumption.
256-Position I2C®-Compatible
Digital Potentiometer
AD5245
FUNCTIONAL BLOCK DIAGRAM
VDD
SCL
SDA
AD0
I2C INTERFACE
A
W
WIPER
REGISTER
POR
GND
Figure 1.
B
PIN CONFIGURATION
W1
8A
VDD 2 AD5245 7 B
GND 3 TOP VIEW 6 AD0
SCL 4 (Not to Scale) 5 SDA
Figure 2.
Operating from a 2.7 V to 5.5 V power supply and consuming
less than 8 µA allows usage in portable battery-operated
applications.
Note that the terms digital potentiometer, VR, and RDAC are
used interchangeably.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2006 Analog Devices, Inc. All rights reserved.
1 page  
TIMING CHARACTERISTICS
5 KΩ, 10 KΩ, 50 KΩ, 100 KΩ VERSIONS
VDD = 5 V ± 10% or 3 V ± 10%, VA = VDD, VB = 0 V, –40°C < TA < +125°C, unless otherwise noted.
Table 3.
Parameter
Symbol Conditions
I2C INTERFACE TIMING CHARACTERISTICS2, 3, 4 (Specifications Apply to All Parts)
SCL Clock Frequency
fSCL
tBUF Bus Free Time Between STOP and START
t1
tHD;STA Hold Time (Repeated START)
t2 After this period, the first clock
pulse is generated.
tLOW Low Period of SCL Clock
t3
tHIGH High Period of SCL Clock
t4
tSU;STA Setup Time for Repeated START Condition
t5
tHD;DAT Data Hold Time
t6
tSU;DAT Data Setup Time
t7
tF Fall Time of Both SDA and SCL Signals
t8
tR Rise Time of Both SDA and SCL Signals
t9
tSU;STO Setup Time for STOP Condition
t10
1 Typical specifications represent average readings at 25°C and VDD = 5 V.
2 Guaranteed by design and not subject to production test.
3 See timing diagram (Figure 44) for locations of measured values.
4 Standard I2C mode operation guaranteed by design.
AD5245
Min Typ1 Max Unit
400 kHz
1.3 µs
0.6 µs
1.3 µs
0.6 µs
0.6 µs
0.9 µs
100 ns
300 ns
300 ns
0.6 µs
Rev. B | Page 5 of 20
5 Page 
REF LEVEL
–5.000dB
–5.5
–6.0
–6.5
/DIV
0.500dB
5kΩ – 1.026MHz
10kΩ – 511kHz
50kΩ – 101kHz
100kΩ – 54kHz
–7.0
–7.5
–8.0
–8.5
–9.0
–9.5
R = 100kΩ
R = 50kΩ
R = 10kΩ
R = 5kΩ
–10.0
–10.5
10k
100k
1M 10M
START 1 000.000Hz
STOP 1 000 000.000Hz
Figure 22. –3 dB Bandwidth @ Code = 0x80
60
CODE = 0x80, VA= VDD, VB = 0V
40
PSRR @ VDD = 3V DC ±10% p-p AC
20
PSRR @ VDD = 5V DC ±10% p-p AC
0
100
1k 10k 100k
FREQUENCY (Hz)
Figure 23. PSRR vs. Frequency
1M
900
800
700
600
500
400
300
200
100
0
10k
VDD = 5V
CODE = 0x55
CODE = 0xFF
100k
1M
FREQUENCY (Hz)
Figure 24. IDD vs. Frequency
10M
AD5245
1 VW
SCL
2
Ch 1 200mV BW Ch 2 5.00 V BW M 100ns A CH2 3.00 V
Figure 25. Large Signal Settling Time, Code 0xFF ≥ 0x00
VA = 5V
VB = 0V
1 VW
SCL
2
Ch 1 100mV BW Ch 2 5.00 V BW M 200ns A CH1 152mV
Figure 26. Digital Feedthrough
VA = 5V
VB = 0V
1 VW
SCL
2
Ch 1 5.00V BW Ch 2 5.00 V BW M 200ns A CH1 3.00 V
Figure 27. Midscale Glitch, Code 0x80 ≥ 0x7F
Rev. B | Page 11 of 20
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD5245.PDF ] | |
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