PDF AD5231 Data sheet ( Hoja de datos )

Número de pieza	AD5231
Descripción	1024-Position Digital Potentiometer
Fabricantes	Analog Devices
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Data Sheet Nonvolatile Memory, 1024-Position Digital Potentiometer AD5231 FEATURES 1024-position resolution Nonvolatile memory maintains wiper setting Power-on refresh with EEMEM setting EEMEM restore time: 140 µs typ Full monotonic operation 10 kΩ, 50 kΩ, and 100 kΩ terminal resistance Permanent memory write protection Wiper setting readback Predefined linear increment/decrement instructions Predefined ±6 dB/step log taper increment/decrement instructions SPI®-compatible serial interface 3 V to 5 V single-supply or ±2.5 V dual-supply operation 28 bytes extra nonvolatile memory for user-defined data 100-year typical data retention, TA = 55°C APPLICATIONS Mechanical potentiometer replacement Instrumentation: gain, offset adjustment Programmable voltage to current conversion Programmable filters, delays, time constants Programmable power supply Low resolution DAC replacement Sensor calibration FUNCTIONAL BLOCK DIAGRAM CS CLK SDI ADDR DECODE SDI RDAC REGISTER AD5231 RDAC GND SERIAL INTERFACE EEMEM(0) VDD A W B SDO WP RDY PR SDO EEMEM CONTROL 28 BYTES USER EEMEM DIGITAL REGISTER EEMEM(1) Figure 1. 100 RWA 2 DIGITAL OUTOUT BUFFER RWB O1 O2 VSS 75 50 25 GENERAL DESCRIPTION The AD5231 is a nonvolatile memory1, digitally controlled potentiometer2 with 1024-step resolution. The device performs the same electronic adjustment function as a mechanical potentiometer with enhanced resolution, solid state reliability, and remote controllability. The AD5231 has versatile programming that uses a standard 3-wire serial interface for 16 modes of operation and adjustment, including scratchpad programming, memory storing and restoring, increment/decrement, ±6 dB/step log taper adjustment, wiper setting readback, and extra EEMEM for user-defined information, such as memory data for other components, look-up table, or system identification information. In scratchpad programming mode, a specific setting can be programmed directly to the RDAC register that sets the 1 The terms nonvolatile memory and EEMEM are used interchangeably. 2 The terms digital potentiometer and RDAC are used interchangeably. Rev. D Document Feedback Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibilityisassumedbyAnalogDevices for itsuse,nor foranyinfringementsofpatentsor other rights of third parties that may result from its use. Specifications subject to change without notice. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners. 0 0 256 512 768 1023 CODE (Decimal) Figure 2. RWA (D) and RWB (D) vs. Decimal Code resistance between Terminals W–A and Terminals W–B. This setting can be stored into the EEMEM and is transferred automatically to the RDAC register during system power-on. The EEMEM content can be restored dynamically or through external PR strobing, and a WP function protects EEMEM contents. To simplify the programming, the linear-step increment or decrement commands can be used to move the RDAC wiper up or down, one step at a time. The ±6 dB step commands can be used to double or half the RDAC wiper setting. The AD5231 is available in a 16-lead TSSOP. The part is guaranteed to operate over the extended industrial temperature range of −40°C to +85°C. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781.329.4700 ©2001–2013 Analog Devices, Inc. All rights reserved. Technical Support www.analog.com 1 page Data Sheet AD5231 TIMING CHARACTERISTICS—10 kΩ, 50 kΩ, 100 kΩ VERSIONS VDD = 3 V to 5.5 V, VSS = 0 V, and −40°C < TA < +85°C, unless otherwise noted. Table 2. Parameter INTERFACE TIMING CHARACTERISTICS2, 3 Clock Cycle Time (tCYC) CS Setup Time CLK Shutdown Time to CS Rise Input Clock Pulse Width Data Setup Time Data Hold Time CS to SDO-SPI Line Acquire CS to SDO-SPI Line Release CLK to SDO Propagation Delay4 CLK to SDO Data Hold Time CS High Pulse Width5 CS High to CS High5 RDY Rise to CS Fall CS Rise to RDY Fall Time Store/Read EEMEM Time6 Power-On EEMEM Restore Time Dynamic EEMEM Restore Time WP High or Low to CS Fall Time CS Rise to Clock Rise/Fall Setup Preset Pulse Width (Asynchronous) Preset Response Time to Wiper Setting FLASH/EE MEMORY RELIABILITY Endurance7 Data Retention8 Symbol t1 t2 t3 t4, t5 t6 t7 t8 t9 t10 t11 t12 t13 t14 t15 t16 tEEMEM1 tEEMEM2 tWP t17 tPRW tPRESP Conditions Clock level high or low From positive CLK transition From positive CLK transition RP = 2.2 kΩ, CL < 20 pF RP = 2.2 kΩ, CL < 20 pF Applies to instructions 0x2, 0x3, and 0x9 RAB = 10 kΩ RAB = 10 kΩ Not shown in timing diagram PR pulsed low to refresh wiper positions Min Typ1 Max Unit 20 ns 10 ns 1 tCYC 10 ns 5 ns 5 ns 40 ns 50 ns 50 ns 0 ns 10 ns 4 tCYC 0 ns 0.1 0.15 ms 25 ms 140 μs 140 μs 40 ns 10 ns 50 70 ns μs 100 100 kCycles Years 1 Typical values represent average readings at 25°C and VDD = 5 V. 2 Guaranteed by design and not subject to production test. 3 See timing diagrams (Figure 3 and Figure 4) for location of measured values. All input control voltages are specified with tR = tF = 2.5 ns (10% to 90% of 3 V) and timed from a voltage level of 1.5 V. Switching characteristics are measured using both VDD = 3 V and VDD = 35 V. 4 Propagation delay depends on the value of VDD, RPULL-UP, and CL. 5 Valid for commands that do not activate the RDY pin. 6 RDY pin low only for Instructions 2, 3, 8, 9, 10, and the PR hardware pulse: CMD_2, 3 ~ 20 ms; CMD_8 ~ 1 ms; CMD_9, 10 ~ 0.12 ms. Device operation at TA = −40°C and VDD < 3 V extends the EEMEM store time to 35 ms. 7 Endurance is qualified to 100,000 cycles per JEDEC Standard 22, Method A117 and measured at −40°C, +25°C, and +85°C; typical endurance at +25°C is 700,000 cycles. 8 Retention lifetime equivalent at junction temperature (TJ) = 55°C per JEDEC Standard 22, Method A117. Retention lifetime based on an activation energy of 0.6 eV derates with junction temperature, as shown in Figure 45 in the Flash/EEMEM Reliability section. Rev. D \| Page 5 of 28 5 Page Data Sheet 0 CODE = 0x200 –10 0x100 0x80 –20 0x40 0x20 –30 0x10 –40 0x08 0x04 –50 0x02 0x01 –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 18. Gain vs. Frequency vs. Code, RAB = 50 kΩ (Figure 32) 0 CODE = 0x200 –10 0x100 0x80 –20 0x40 0x20 –30 0x10 –40 0x08 0x04 –50 0x02 0x01 –60 1k 10k 100k 1M FREQUENCY (Hz) Figure 19. Gain vs. Frequency vs. Code, RAB = 100 kΩ (Figure 32) 80 RAB = 100kΩ 70 RAB = 50kΩ 60 RAB = 10kΩ 50 40 30 20 10 VDD = 5.0V ±100mV AC VSS = 0V, VA = 5V, VB = 0V MEASURED AT VW WITH CODE = 0x200 0 100 1k 10k 100k FREQUENCY (Hz) 1M Figure 20. PSRR vs. Frequency 10M AD5231 VDD = 5V 100 VA = 2.25V VB = 0V 90 10 0% EXPECTED VALUE MIDSCALE VA VW 0.5V/DIV 100µs/DIV Figure 21. Power-On Reset, VA = 2.25 V, VB = 0 V, Code = 1010101010B 2.55 VDD/VSS = 5V/0V CODE = 0x200 TO 0x1FF 2.53 2.51 2.49 RAB = 10kΩ RAB = 50kΩ RAB = 100kΩ 2.47 2.45 0 5 10 15 20 25 TIME (µs) Figure 22. Midscale Glitch Energy, Code 0x200 to 0x1FF 5V/DIV CS CLK 5V/DIV SDI 5V/DIV IDD 20mA/DIV 4ms/DIV Figure 23. IDD vs. Time when Storing Data to EEMEM Rev. D \| Page 11 of 28 11 Page

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