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PDF AD7399 Data sheet ( Hoja de datos )
| Número de pieza | AD7399 | |
| Descripción | Quad/ Serial-Input 12-Bit/10-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7399 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
AD7398—12-Bit Resolution
AD7399—10-Bit Resolution
Programmable Power Shutdown
Single (3 V to 5 V) or Dual (؎5 V) Supply Operation
3-Wire Serial SPI-Compatible Interface
Internal Power ON Reset
Double Buffered Registers for Simultaneous
Multichannel DAC Update
Four Separate Rail-to-Rail Reference Inputs
Thin Profile TSSOP-16 Package Available
Low Tempco 1.5 ppm/؇C
APPLICATIONS
Automotive Output Voltage Span
Portable Communications
Digitally Controlled Calibration
PC Peripherals
GENERAL DESCRIPTION
The AD7398/AD7399 family of quad, 12-bit/10-bit, voltage-
output digital-to-analog converters is designed to operate from a
single 3 V to 5 V or a dual ±5 V supply. Built with Analog’s robust
CBCMOS process, this monolithic DAC offers the user low
cost, and ease-of-use in single or dual-supply systems.
The applied external reference VREF determines the full-scale
output voltage. Valid VREF values include VSS < VREF < VDD that
result in a wide selection of full-scale outputs. For multiplying
applications ac inputs can be as large as ± 5 VP.
A doubled-buffered serial-data interface offers high-speed,
3-wire, SPI and microcontroller-compatible inputs using serial-
data-in (SDI), clock (CLK), and a chip-select (CS). A common
level-sensitive load-DAC strobe (LDAC) input allows simulta-
neous update of all DAC outputs from previously loaded Input
Registers. Additionally, an internal power ON reset forces the
output voltage to zero at system turn ON. An external asynchro-
nous reset (RS) also forces all registers to the zero code state. A
programmable power-shutdown feature reduces power dissipa-
tion on unused DACs.
Both parts are offered in the same pinout to enable users to
select the appropriate resolution for their application without
redesigning the layout. For 8-bit resolution applications see the
pin compatible AD7304 product.
The AD7398/AD7399 is specified over the extended industrial
(–40°C to +125°C) temperature range. Parts are available in
wide body SOIC-16 and ultracompact thin 1.1 mm TSSOP-
16 packages.
Quad, Serial-Input
12-Bit/10-Bit DACs
AD7398/AD7399
FUNCTIONAL BLOCK DIAGRAM
VDD
VREFB VREFA
SERIAL
REGISTER
CS
SDI
CLK
INPUT
REG A
DAC A
REGISTER
DAC A
INPUT
REG B
DAC B
REGISTER
DAC B
INPUT
REG C
DAC C
REGISTER
DAC C
VOUTA
VOUTB
VOUTC
12/10
POWER
ON RESET
INPUT
REG D
DAC D
REGISTER
DAC D
VOUTD
VSS RS
LDAC VREFC VREFD GND
0.50
0.40
0.30
0.20
VDD = +5V
VSS = –5V
VREF = +2.5V
TA = 25؇C
0.10
0
–0.10
–0.20
–0.30
–0.40
–0.50
0
512 1024 1536 2048 2560 3072 3584 4096
CODE – Decimal
Figure 1. AD7398 DNL vs. Code (TA = 25°C)
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
PIN CONFIGURATION
VOUTB 1
16 VOUTC
VOUTA 2
15 VOUTD
VSS 3
AD7398/
AD7399
14 VDD
VREFA 4
13 VREFC
TOP VIEW
VREFB 5 (Not to Scale) 12 VREFD
GND 6
11 SDI
LDAC 7
10 CLK
RS 8
9 CS
AD7398/AD7399
Pin No.
1
2
3
4
5
6
7
8
9
10
11
12
13
14
15
16
Mnemonic
VOUTB
VOUTA
VSS
VREFA
VREFB
GND
LDAC
RS
CS
CLK
SDI
VREFD
VREFC
VDD
VOUTD
VOUTC
PIN FUNCTION DESCRIPTIONS
Function
DAC B Voltage Output.
DAC A Voltage Output.
Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.
DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can
be tied to VDD or VSS pin.
DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can
be tied to VDD or VSS pin.
Ground Pin.
Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to
DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.
Resets Input and DAC Registers to All Zero Codes. Shift Register contents unchanged.
Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Regis-
ter Data to the Input Register when CS returns High. Does not effect LDAC operation.
Schmitt Triggered Clock Input, Positive Edge Clocks Data into Shift Register.
Serial Data Input. Input data loads directly into the shift register.
DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can
be tied to VDD or VSS pin.
DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can
be tied to VDD or VSS pin.
Positive Power Supply Input. Specified range of operation 3 V to 5 V ± 10%.
DAC D Voltage Output.
DAC C Voltage Output.
REV. 0
–5–
5 Page 
3.0
AD7398/AD7399
2.5 VDD = +5V
VSS = –5V
2.0
1.5
1.0
0.5
0
–50
0 50 100
TEMPERATURE – ؇C
150
TPC 17. Supply Current vs. Temperature
36
AD7398/AD7399
VDD = +5V
35 VSS = –5V
34
33
32
31
–60 –40 –20
0 20 40 60 80 100 120 140
TEMPERATURE – ؇C
TPC 18. Shutdown Current vs. Temperature
1.0
0.75
AD7398
SAMPLE SIZE = 135
VREF = 2.5V
AD7398/AD7399
0.5 CODE = FFFH
0.25
CODE = 000H
0
0 100 200 300 400 500
HOURS OF OPERATION AT 150؇C
TPC 19. AD7398 Long-Term Drift
600
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7399.PDF ] | |
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