PDF AD7392 Data sheet ( Hoja de datos )

Número de pieza	AD7392
Descripción	+3 V/ Parallel Input Micropower 10- and 12-Bit DACs
Fabricantes	Analog Devices
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No Preview Available ! a +3 V, Parallel Input Micropower 10- and 12-Bit DACs FEATURES Micropower: 100 ␮A 0.1 ␮A Typical Power Shutdown Single-Supply +2.7 V to +5.5 V Operation Compact 1.1 mm Height TSSOP-20 Package AD7392/12-Bit Resolution AD7393/10-Bit Resolution 0.9 LSB Differential Nonlinearity Error APPLICATIONS Automotive 0.5 V to 4.5 V Output Span Voltage Portable Communications Digitally Controlled Calibration PC Peripherals AD7392/AD7393 FUNCTIONAL BLOCK DIAGRAM AD7392 VREF 12-BIT DAC 12 DAC REGISTER 12 DGND CS DB0–DB11 RS VDD VOUT SHDN AGND GENERAL DESCRIPTION The AD7392/AD7393 family of 10- and 12-bit voltage-output digital-to-analog converters is designed to operate from a single +3 V supply. Built using a CBCMOS process, these monolithic DACs offer the user low cost and ease of use in single-supply +3 V systems. Operation is guaranteed over the supply voltage range of +2.7 V to +5.5 V, making this device ideal for battery operated applications. The full-scale voltage output is determined by the external reference input voltage applied. The rail-to-rail REFIN to DACOUT allows for a full-scale voltage set equal to the positive supply VDD or any value in between. The voltage outputs are capable of sourcing 5 mA. A 12-bit wide data latch loads with a 45 ns write time allowing interface to the fastest processors without wait states. 1 AD7392 0.8 0.6 0.4 VDD = +2.7V VREF = +2.5V TA = 25؇C 0.2 0 ؊0.2 ؊0.4 ؊0.6 ؊0.8 ؊1 0 512 1024 1536 2048 2560 3072 3584 4096 CODE – Decimal Figure 1. AD7392 Differential Nonlinearity Error vs. Code Additionally, an asynchronous RS input sets the output to zero scale at power on or upon user demand. Both parts are offered in the same pinout to allow users to select the amount of resolution appropriate for their applications without circuit card changes. The AD7392/AD7393 are specified for operation over the ex- tended industrial (–40°C to +85°C) temperature range. The AD7393AR is specified for the –40°C to +125°C automotive temperature range. AD7392/AD7393s are available in plastic DIP, and 20-lead SOIC packages. The AD7393ARU is avail- able for ultracompact applications in a thin 1.1 mm height TSSOP-20 package. For serial data input, 8-lead packaged versions, see the AD7390 and AD7391 products. 1 AD7393 0.8 0.6 0.4 VDD = +2.7V VREF = +2.5V TA = 25؇C 0.2 0 ؊0.2 ؊0.4 ؊0.6 ؊0.8 ؊1 0 128 256 384 512 640 768 896 1024 CODE – Decimal Figure 2. AD7393 Differential Nonlinearity Error vs. Code REV. A Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1999 1 page Typical Performance Characteristics–AD7392/AD7393 1 AD7392 0.8 0.6 0.4 VDD = 2.7V VREF = 2.5V TA = 25؇C 0.2 0 –0.2 –0.4 –0.6 –0.8 –1 0 512 1024 1536 2048 2560 3072 3584 4096 CODE – Decimal Figure 5. AD7392 Integral Nonlinear- ity Error vs. Code 1 AD7393 0.8 0.6 0.4 0.2 0 –0.2 –0.4 –0.6 –0.8 VDD = 2.7V VREF = 2.5V TA = 25؇C –1 0 128 256 384 512 640 768 896 1024 CODE – Decimal Figure 6. AD7393 Integral Nonlinear- ity Error vs. Code 25 AD7392 SS = 100 UNITS 20 TA = 25؇C VDD = 2.7V VREF = 2.5V 15 10 5 0 5.0 5.8 6.6 7.3 8.1 8.9 9.7 10.5 11.2 12.0 TOTAL UNADJUSTED ERROR – LSB Figure 7. AD7392 Total Unadjusted Error Histogram 100 AD7393 90 SS = 300 UNITS 80 TA = 25؇C VDD = 2.7V 70 VREF = 2.5V 60 50 40 30 20 10 0 –10 –3.3 3.3 10 16 23 30 36 43 50 TOTAL UNADJUSTED ERROR – LSB Figure 8. AD7393 Total Unadjusted Error Histogram 30 AD7393 SS = 100 UNITS 24 TA = ؊40؇ to 85؇C VDD = 2.7V VREF = 2.5V 18 12 6 0 –66 –60 –52 –46 –40 –32 –26 –20 –12 –6 0 FULL SCALE TEMPCO – ppm/؇C Figure 9. AD7393 Full-Scale Output Tempco Histogram 16 AD7392 14 VDD = 5V VREF = 2.5V 12 TA = 25؇C 10 8 6 4 2 0 1 10 100 1k 10k 100k FREQUENCY – Hz Figure 10. Voltage Noise Density vs. Frequency 100 AD7392 95 TA = 25؇C 90 VDD = 3.0V 85 VLOGIC FROM 0V TO 3.0V 80 75 VLOGIC FROM 70 3.0V TO 0V 65 60 55 50 0.0 0.5 1.0 1.5 2.0 2.5 3.0 VIN – Volts Figure 11. Supply Current vs. Logic Input Voltage 5.0 AD7392 4.5 CODE = FFFH 4.0 VREF = 2V RS LOGIC VOLTAGE 3.5 VARIED 3.0 VLOGIC FROM 2.5 HIGH TO LOW 2.0 1.5 1.0 VLOGIC FROM LOW TO HIGH 0.5 0.0 1 23 45 6 SUPPLY VOLTAGE – V 7 Figure 12. Logic Threshold vs. Supply Voltage 100 AD7392 90 SAMPLE SIZE = 300 UNITS 80 VDD = 5.0V, VLOGIC = 0V VDD = 3.6V, VLOGIC = 2.4V 70 60 50 VDD = 3.0V, VLOGIC = 0V 40 30 20 ؊55 ؊35 ؊15 5 25 45 65 85 105 125 TEMPERATURE – ؇C Figure 13. Supply Current vs. Temperature REV. A –5– 5 Page REV. A OUTLINE DIMENSIONS Dimensions shown in inches and (mm). 20-Lead Plastic DIP Package (N-20) 1.060 (26.90) 0.925 (23.50) 20 1 PIN 1 0.210 (5.33) MAX 0.160 (4.06) 0.115 (2.93) 0.022 (0.558) 0.014 (0.356) 0.100 (2.54) BSC 11 0.280 (7.11) 10 0.240 (6.10) 0.060 (1.52) 0.015 (0.38) 0.325 (8.25) 0.300 (7.62) 0.195 (4.95) 0.115 (2.93) 0.130 (3.30) MIN 0.070 (1.77) SEATING 0.045 (1.15) PLANE 0.015 (0.381) 0.008 (0.204) AD7392/AD7393 20-Lead SOIC Package (R-20) 0.5118 (13.00) 0.4961 (12.60) 20 11 1 10 PIN 1 0.1043 (2.65) 0.0926 (2.35) 0.0291 0.0098 (0.74) (0.25) x 45° 0.0118 (0.30) 0.0040 (0.10) 8° 0.0500 0.0192 (0.49) (1.27) 0.0138 (0.35) BSC SEATING PLANE 0.0125 (0.32) 0° 0.0091 (0.23) 0.0500 (1.27) 0.0157 (0.40) 20-Lead Thin Surface Mount TSSOP Package (RU-20) 0.260 (6.60) 0.252 (6.40) 20 11 1 10 0.006 (0.15) 0.002 (0.05) SEATING PLANE PIN 1 0.0256 (0.65) BSC 0.0433 (1.10) MAX 8° 0.0118 (0.30) 0° 0.0075 (0.19) 0.0079 (0.20) 0.0035 (0.090) 0.028 (0.70) 0.020 (0.50) –11– 11 Page

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