AD73322L Datasheet PDF - Analog Devices
| Part Number | AD73322L | |
| Description | Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End | |
| Manufacturers | Analog Devices | |
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a Low Cost, Low Power CMOS
General-Purpose Dual Analog Front End
AD73322L
FEATURES
Two 16-Bit A/D Converters
Two 16-Bit D/A Converters
Programmable Input/Output Sample Rates
78 dB ADC SNR
78 dB DAC SNR
64 kS/s Maximum Sample Rate
–90 dB Crosstalk
Low Group Delay (25 s Typ per ADC Channel,
50 s Typ per DAC Channel)
Programmable Input/Output Gain
Flexible Serial Port which Allows Up to Four Dual
Codecs to be Connected in Cascade Giving Eight
I/O Channels
Single (2.7 V to 3.3 V) Supply Operation
50 mW Typ Power Consumption at 3.0 V
Temperature Range: –40؇C to +105؇C
On-Chip Reference
28-Lead SOIC, TSSOP, and 44-Lead LQFP Packages
APPLICATIONS
General-Purpose Analog I/O
Speech Processing
Cordless and Personal Communications
Telephony
Active Control of Sound and Vibration
Data Communications
Wireless Local Loop
VFBP1
VINP1
VINN1
VFBN1
VOUTP1
VOUTN1
REFOUT
REFCAP
VFBP2
VINP2
VINN2
VFBN2
VOUTP2
VOUTN2
FUNCTIONAL BLOCK DIAGRAM
AVDD1 AVDD2
DVDD
AD73322L
ADC CHANNEL 1
SDI
SDIFS
DAC CHANNEL 1
REFERENCE
SPORT
SCLK
SE
RESET
ADC CHANNEL 2
MCLK
DAC CHANNEL 2
SDOFS
SDO
AGND1 AGND2 DGND
GENERAL DESCRIPTION
The AD73322L is a dual front-end processor for general pur-
pose applications including speech and telephony. It features
two 16-bit A/D conversion channels and two 16-bit D/A con-
version channels. Each channel provides 78 dB signal-to-noise
ratio over a voiceband signal bandwidth. It also features an
input-to-output gain network in both the analog and digital
domains. This is featured on both codecs and can be used for
impedance matching or scaling when interfacing to Subscriber
Line Interface Circuits (SLICs).
The AD73322L is particularly suitable for a variety of applica-
tions in the speech and telephony area, including low bit rate,
high quality compression, speech enhancement, recognition and
synthesis. The low group delay characteristic of the part makes
it suitable for single or multichannel active control applications.
The A/D and D/A conversion channels feature programmable
input/output gains with ranges 38 dB and 21 dB respectively.
An on-chip reference voltage is included to allow single-
supply operation.
The sampling rate of the codecs is programmable with four
separate settings offering 64 kHz, 32 kHz, 16 kHz, and 8 kHz
sampling rates (from a master clock of 16.384 MHz).
A serial port (SPORT) allows easy interfacing of single or cas-
caded devices to industry standard DSP engines. The SPORT
transfer rate is programmable to allow interfacing to both fast
and slow DSP engines.
The AD73322L is available in 28-lead SOIC, 28-lead TSSOP,
and 44-lead LQFP packages.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
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AD73322L
VREFCAP
VREFOUT
ADC
DAC
Table II. Signal Ranges
Maximum Input Range at VIN
Nominal Reference Level
Maximum Voltage Output Swing
Single-Ended
Differential
Nominal Voltage Output Swing
Single-Ended
Differential
Output Bias Voltage
3 V Power Supply
5VEN = 0
1.2 V ± 10%
1.2 V ± 10%
1.578 V p-p
1.0954 V p-p
1.578 V p-p
3.156 V p-p
1.0954 V p-p
2.1909 V p-p
VREFOUT
TIMING CHARACTERISTICS (AVDD = 3 V ؎ 10%; DVDD = 3 V ؎ 10%; AGND = DGND = 0 V; TA = TMlN to TMAX, unless
otherwise noted.)
Parameter
Limit at
TA = –40؇C to +105؇C
Clock Signals
t1
t2
t3
Serial Port
t4
t5
t6
t7
t8
t9
t10
t11
t12
t13
61
24.4
24.4
t1
0.4 × t1
0.4 × t1
20
0
10
10
10
10
30
Specifications subject to change without notice.
Unit
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns min
ns max
ns max
Description
See Figure 1
MCLK Period
MCLK Width High
MCLK Width Low
See Figures 3 and 4
SCLK Period
SCLK Width High
SCLK Width Low
SDI/SDIFS Setup Before SCLK Low
SDI/SDIFS Hold After SCLK Low
SDOFS Delay from SCLK High
SDOFS Hold After SCLK High
SDO Hold After SCLK High
SDO Delay from SCLK High
SCLK Delay from MCLK
REV. 0
–5–
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Part DetailsOn this page, you can learn information such as the schematic, equivalent, pinout, replacement, circuit, and manual for AD73322L electronic component. |
| Information | Total 40 Pages | |
| Link URL | [ Copy URL to Clipboard ] | |
| Download | [ AD73322L.PDF Datasheet ] | |
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Featured Datasheets
| Part Number | Description | MFRS |
| AD73322 | The function is Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End. Analog Devices | |
| AD73322L | The function is Low Cost/ Low Power CMOS General-Purpose Dual Analog Front End. Analog Devices | |
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