|
|
PDF AD7010 Data sheet ( Hoja de datos )
| Número de pieza | AD7010 | |
| Descripción | CMOS JDC p/4 DQPSK Baseband Transmit Port | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7010 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
a CMOS
JDC /4 DQPSK Baseband Transmit Port
AD7010
FEATURES
Single +5 V Supply
On-Chip /4 DQPSK Modulator
Root-Raised-Cosine Tx Filters, ␣ = 0.5
Two 10-Bit D/A Converters
4th Order Reconstruction Filters
Differential Analog Outputs
On-Chip Ramp Up/Down Power Control
On-Chip Tx Offset Calibration
Very Low Power Dissipation, 30 mW typ
Power Down Mode < 5 A
On-Chip Voltage Reference
24-Pin SSOP
APPLICATIONS
Japanese Digital Cellular Telephony
GENERAL DESCRIPTION
The AD7010 is a complete low power, CMOS, π/4 DQPSK
modulator with single +5 V power supply. The part is designed
to perform the baseband conversion of I and Q transmit
waveforms in accordance with the Japanese Digital Cellular
Telephone system.
The on-chip π/4 Differential Quadrature Phase Shift Keying
(DQPSK) digital modulator, which includes the Root Raised
Cosine filters, generates I and Q data in response to the transmit
data stream. The AD7010 also contains ramp control envelope
logic to shape the I and Q output waveforms when ramping up
or down at the beginning or end of a transmit burst.
Besides providing all the necessary logic to perform π/4 DQPSK
modulation, the part also provides reconstruction filters to
smooth the DAC outputs, providing continuous time analog
outputs. The AD7010 generates differential analog outputs for
both the I and Q signals.
As it is a necessity for all digital mobile systems to use the lowest
possible power, the device has power down options. The
AD7010 is housed in a space efficient 24-pin SSOP (Shrink
Small Outline Package).
POWER
Tx DATA
Tx CLK
READY
BIN
FUNCTIONAL BLOCK DIAGRAM
DGND
VDD
VAA AGND
π/4 DQPSK
MODULATOR
AD7010
10-BIT
I-DAC
RECONSTRUCTION
FILTERS
CALIBRATION CIRCUITRY
10-BIT
Q-DAC
RECONSTRUCTION
FILTERS
2.46V
REFERENCE
ITx
ITx
QTx
QTx
BOUT
MCLK
BYPASS
MODE1 MODE2
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7010
PIN FUNCTION DESCRIPTION
SSOP Pin
Number
Mnemonic
Function
POWER SUPPLY
19
5
14, 18, 23
VAA
VDD
AGND
6 DGND
Positive power supply for analog section.
Positive power supply for digital section, both supplies should be externally tied together.
Analog ground for transmit section.
Digital ground for transmit section, both grounds should be externally tied together.
ANALOG SIGNAL AND REFERENCE
13
BYPASS
Reference decoupling output. A decoupling capacitor should be connected between this pin a
and AGND.
16, 17
ITx, ITx
Differential analog outputs for the I channel, representing true and complementary outputs
of the I waveform.
21, 20
QTx, QTx
Differential analog outputs for the Q channel, representing true and complementary outputs
of the Q waveform.
TRANSMIT INTERFACE AND CONTROL
7
MCLK
Master clock, digital input. This pin should be driven by a 2.688 MHz CMOS compatible
clock source in digital mode.
3
TxCLK
This is a digital output, transmit clock. This may be used to clock in transmit data at 42 kHz.
4
TxDATA
This is a digital input. This pin is used to clock in transmit data on the falling edge of TxCLK
at a rate of 42 kHz.
2 BIN This is a digital input. This input is used to initiate the ramping up (BIN high) or down (BIN
low) of the I and Q waveforms.
24
BOUT
Burst out, digital output. This is the BIN input delayed by the pipeline delay, both digital and
analog, of the AD7010. This can be used to turn on and off the RF amplifiers in synchroniza-
tion with the I and Q waveforms.
1
POWER
Transmit sleep mode, digital input. When this goes low, the AD7010 goes into sleep mode,
drawing minimal current. When this pin goes high, the AD7010 is brought out of sleep mode
and initiates a self-calibration routine to eliminate the offset between ITx & ITx and the offset
between QTx & QTx.
12
READY
Transmit ready, digital output. This output goes high once the self-calibration routine is complete.
9, 11
MODE1,
MODE2
Mode control, digital inputs. These are used to enter the AD7010 into three different
operating modes, see Table I.
8, 10, 15, 22 NC
No Connects. These pins are no connects and should not be used as routes for other circuit signals.
SSOP PIN CONFIGURATION
POWER 1
BIN 2
TxCLK 3
24 BOUT
23 AGND
22 NC
TxDATA 4
21 QTx
VDD
DGND
5
6
MCLK 7
NC 8
20 QTx
AD7010
TOP VIEW
(Not to Scale)
19 VAA
18 AGND
17 ITx
MODE1 9
16 ITx
NC 10
15 NC
MODE2 11
14 AGND
READY 12
13 BYPASS
REV. B
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD7010.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7010 | CMOS JDC p/4 DQPSK Baseband Transmit Port | Analog Devices |
| AD7011 | CMOS/ ADC p/4 DQPSK Baseband Transmit Port | Analog Devices |
| AD7013 | CMOS TIA IS-54 Baseband Receive Port | Analog Devices |
| AD7015 | BASEBAND CODEC and VOICEBAND CODEC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |