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PDF AD7002 Data sheet ( Hoja de datos )
| Número de pieza | AD7002 | |
| Descripción | LC2MOS GSM Baseband I/O Port | |
| Fabricantes | Analog Devices | |
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FEATURES
Single +5 V Supply
Transmit Channel
On-Chip GMSK Modulator
Two 10-Bit D/A Converters
Analog Reconstruction Filters
Power-Down Mode
Receive Channel
Two Sigma-Delta A/D Converters
FIR Digital Filters
On-Chip Offset Calibration
Power-Down Mode
3 Auxiliary D/A Converters
Power-Down Modes
On-Chip Voltage Reference
Low Power
44-Lead PQFP
APPLICATIONS
GSM
PCN
LC2MOS
GSM Baseband I/O Port
AD7002
GENERAL DESCRIPTION
The AD7002 is a complete low power, two-channel, input/
output port with signal conditioning. The device is used as a
baseband digitization subsystem, performing signal conversion
between the DSP and the IF/RF sections in the Pan-European
telephone system (GSM).
The transmit path consists of an onboard digital modulator,
containing all the code necessary for performing Gaussian Mini-
mum Shift Keying (GMSK), two high accuracy, fast DACs with
output reconstruction filters. The receive path is composed of
two high performance sigma-delta ADCs with digital filtering. A
common bandgap reference feeds the ADCs and signal DACs.
Three control DACs (AUX DAC1 to AUX DAC3) are in-
cluded for such functions as AFC, AGC and carrier signal shap-
ing. In addition, AUX FLAG may be used for routing digital
control information through the device to the IF/RF sections.
As it is a necessity for all GSM mobile systems to use the lowest
power possible, the device has power-down or sleep options for
all sections (transmit, receive and auxiliary).
The AD7002 is housed in 44-lead PQFP (Plastic Quad Flatpack).
Tx SLEEP
Tx DATA
Tx CLK
THREE-STATE
ENABLE
Rx CLK
Rx DATA (I DATA)
Rx SYNC
I/Q (Q DATA)
RATE
MODE
AUX DATA
AUX CLK
AUX LATCH
Rx SLEEP1
Rx SLEEP2
FUNCTIONAL BLOCK DIAGRAM
DVDD DGND
AVDD AGND
GMSK PULSE
SHAPING ROM
10-BIT DAC
4TH ORDER BESSEL
LOW-PASS FILTER
AD7002
10-BIT DAC
2.5V
REFERENCE
4TH ORDER BESSEL
LOW-PASS FILTER
REFERENCE
OUTPUT BUFFER
RECEIVE
CHANNEL
SERIAL
INTERFACE
I CHANNEL
DIGITAL FIR FILTER
OFFSET REGISTER
OFFSET REGISTER
Q CHANNEL
DIGITAL FIR FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
Σ−∆ MODULATOR
SWITCH-CAP
FILTER
I Tx
Q Tx
REF OUT
I Rx
Q Rx
16-BIT SHIFT REGISTER
9-BIT DAC 10-BIT DAC 8-BIT DAC
AUX
DAC 1
AUX
DAC 2
AUX
AUX
DAC 3 FLAG
CAL CLK2
CLK1 MZERO
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1997
1 page  
AD7002
GMSK Phase Trajectory Error
This is a measure of the phase error between the transmitted
phase of an ideal GMSK modulator and the actual phase trans-
mitted by the AD7002, when transmitting a random sequence
of data bits. It is specified as a peak phase error and also as an
rms phase error.
Group Delay Linearity
The group delay linearity, or differential group delay, is the
group delay over the full band relative to the group delay at one
particular frequency. The reference frequency for the AD7002 is
1 kHz.
Group Delay Between Channels
This is the difference between the group delay of the I and Q
channels and is a measure of the phase matching characteristics
of the two.
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the DAC or ADC transfer function.
Maximum Phase Effect Instance
This is the time at which a transmitted data bit will have its
maximum phase change at the ITx and QTx outputs (see fig-
ure). This time includes the delay in the GMSK modulator and
in the Analog low-pass filters. Maximum phase effect instance is
measured from the Tx CLK falling edge, which latches the data
bit, to the ITx and QTx analog outputs.
90°
45°
0°
DATA BIT
CLOCKED IN BY TxCLK
≈ 9µs
MAXIMUM PHASE
EFFECT INSTANT
Transmit Channel Maximum Phase Effect Instance
Output Rate
This is the rate at which data words are made available at the
Rx DATA pin (Mode 0) or the IDATA and QDATA pins
(Mode 1). There are two rates, depending on whether the de-
vice is operated in RATE0 or RATE1.
Offset Error
This is the amount of offset, w.r.t. VREF in the transmit DACs
and the auxiliary DACs and is expressed in mVs for the Trans-
mit section and in LSBs for the Auxiliary section.
Output Impedance
This is a measure of the drive capability of the auxiliary DAC
outputs and is expressed in kΩs.
Output Signal Span
This is the output signal range for the Transmit Channel section
and the Auxiliary DAC section. For the transmit channel the
span is ± 1.25 volts centered on 2.5 volts, and for the Auxiliary
DAC section it is 0 to +VREF.
Output Signal Full-Scale Accuracy
This is the accuracy of the full-scale output (all 1s loaded to the
DACs) on each transmit channel measured w.r.t. 25 V and is
expressed in dBs.
Phase Matching Between Channels
This is a measure of the phase matching characteristics of the I
and Q transmit channels. It is obtained by transmitting all ones
and then measuring the difference between the actual phase
shift between the I and Q outputs and the ideal phase shift of
90°.
Sampling Rate
This is the rate at which the modulators on the receive channels
sample the analog input.
Settling Time
This is the digital filter settling time in the AD7002 receive
section. On initial power-up, or after returning from the sleep
mode, it is necessary to wait this amount of time to obtain use-
ful data.
Signal Input Span
The input signal range for the I and Q channels is biased about
VREF. It can go ± 1.25 volts about this point.
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal-to-(noise + distortion) at the
output of the receive channel. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all amplitude of the
fundamental. Noise is the rms sum of all nonfundamental sig-
nals up to half the sampling frequency (fS/2), excluding dc. The
ratio is dependent upon the number of quantization levels in the
digitization process; the more levels, the smaller the quantiza-
tion noise. The theoretical signal-to-(noise+distortion) ratio for
a sine wave is given by:
Signal to (Noise + Distortion) = (6.02N + 1.76) dB
REV. B
–5–
5 Page 
AD7002
from the analog modulator, will the output data be correct. The
analog modulator, on coming out of sleep, will generate mean-
ingful data after 21 master clock cycles.
01...111
01...110
00...001
00...000
11...111
11...110
10...001
10...000
–VFULLSCALE
VREF
VIN, INPUT VOLTAGE
+VFULLSCALE
Figure 13. ADC Transfer Function for I and Q Receive
Channels
Calibration
Included in the digital filter is a means by which receive signal
offsets may be calibrated out. Calibration can be effected
through the use of the CAL and MZERO pins.
Each channel of the digital low-pass filter section has an offset
register. The offset register can be made to contain a value
representing the dc offset of the preceding analog circuitry. In
normal operation, the value stored in the offset register is sub-
tracted from the filter output data before the data appears on
the serial output pin. By so doing, the dc offset is cancelled.
In each channel the offset register is cleared (twos complement
zero) when CAL is high and becomes loaded with the first digi-
tal filter result after CAL falls. This result will be a measure of
the channel dc offset if the analog channel is switched to zero
prior to CAL falling. Time must be provided for the analog
circuitry and the digital filter to settle after the analog circuitry is
switched to zero and before CAL falls. The offset register will
then be loaded with the proper representation of the dc offset.
CAL must be high for more than 608 master clock cycles
(CLK1, CLK2). If the analog channels are switched to zero
coincident with CAL rising, this time is also sufficient to satisfy
the settling time of the analog sigma-delta modulators and the
digital filters. CAL may be held high for an unlimited time if
convenient or necessary. Only the digital result following the fall
of CAL will be loaded into each offset register. After CAL falls,
normal operation resumes immediately.
10.00
0.00
–10.00
–20.00
–30.00
–40.00
–50.00
–60.00
–70.00
–80.00
–90.00
–100.00
–110.00
–120.00
–130.00
–140.00
0
100 200 300 400 500 600 700 800 900 1000
FREQUENCY – kHz
Figure 14. Digital Filter Frequency Response
The offset registers are static and retain their contents even
during sleep mode (Rx SLEEP1 and Rx SLEEP2 high). They
need only be updated if drifts in the analog dc offsets are experi-
enced or expected. However, on initial application of power to
the digital supply pins the offset registers may contain grossly
incorrect values and, therefore, calibration must be activated at
least once after power is applied even if the facility of calibration
is not regularly used.
Table II. Truth Table for the MODE and RATE Pins
MODE RATE
00
01
10
11
Data Format
IQ Data
IQ Data
I Data
I Data
I/Q
I/Q
Q Data
Q Data
Output Word Rate
270.8 kHz
541.7 kHz
270.8 kHz
541.7 kHz
The MZERO pin can be used to zero the sigma-delta modula-
tors if calibration of preceding analog circuitry is not required.
Each analog modulator has an internal analog multiplexer con-
trolled by MZERO. With MZERO low, the modulator inputs
are connected to the I Rx and Q Rx pins for normal operation.
With MZERO high, both modulator inputs are connected to the
VREF pin, which is analog ground for the modulators. If calibra-
tion of external analog circuitry is desired, MZERO should be
kept low during the calibration cycle.
Rx SLEEP1
Rx SLEEP2
CAL
RATE, MODE,
THREE- STATE
CONTROL
t38
t40
t39
Figure 15. Calibration and Control Timing Diagram
REV. B
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7002.PDF ] | |
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