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PDF AD679 Data sheet ( Hoja de datos )
| Número de pieza | AD679 | |
| Descripción | 14-Bit 128 kSPS Complete Sampling ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
AC and DC Characterized and Specified
(K, B, T Grades)
128k Conversions per Second
1 MHz Full Power Bandwidth
500 kHz Full Linear Bandwidth
78 dB S/N+D (K, B, T Grades)
Twos Complement Data Format (Bipolar Mode)
Straight Binary Data Format (Unipolar Mode)
10 M⍀ Input Impedance
8-Bit Bus Interface
On-Board Reference and Clock
10 V Unipolar or Bipolar Input Range
Pin Compatible with AD678 12-Bit, 200 kSPS ADC
MIL-STD-883 Compliant Versions Available
14-Bit 128 kSPS
Complete Sampling ADC
AD679
FUNCTIONAL BLOCK DIAGRAM
GENERAL DESCRIPTION
The AD679 is a complete, multipurpose 14-bit monolithic
analog-to-digital converter, consisting of a sample-and-hold am-
plifier (SHA), a microprocessor-compatible bus interface, a volt-
age reference, and clock generation circuitry.
The AD679 is specified for ac (or dynamic) parameters such as
S/N+D ratio, THD, and IMD, which are important in signal
processing applications. In addition, the AD679K, B, and T
grades are fully specified for dc parameters that are important in
measurement applications.
The 14 data bits are accessed in two read operations (8 + 6),
with left justification. Data format is straight binary for unipolar
mode and twos complement binary for bipolar mode. The input
has a full-scale range of 10 V with a full power bandwidth of
1 MHz and a full linear bandwidth of 500 kHz. High input
impedance (10 MΩ) allows direct connection to unbuffered
sources without signal degradation. Conversions can be initiated
either under microprocessor control or by an external clock
asynchronous to the system clock.
This product is fabricated on Analog Devices’ BiMOS process,
combining low power CMOS logic with high precision, low
noise bipolar circuits; laser-trimmed thin-film resistors provide
high accuracy. The converter utilizes a recursive subranging
algorithm that includes error correction and flash converter
circuitry to achieve high speed and resolution.
The AD679 operates from +5 V and ±12 V supplies and dissipates
560 mW (typ). The part is available in 28-lead plastic DIP,
ceramic DIP, and 44 J-leaded ceramic surface-mount packages.
PRODUCT HIGHLIGHTS
1. COMPLETE INTEGRATION: The AD679 minimizes
external component requirements by combining a high
speed sample-and-hold amplifier (SHA), ADC, 5 V refer-
ence, clock, and digital interface on a single chip. This
provides a fully specified sampling A/D function unattain-
able with discrete designs.
2. SPECIFICATIONS: The AD679K, B, and T grades provide
fully specified and tested ac and dc parameters. The AD679J,
A, and S grades are specified and tested for ac parameters; dc
accuracy specifications are shown as typicals. DC specifica-
tions (such as INL, gain, and offset) are important in control
and measurement applications. AC specifications (such as
S/N+D ratio, THD, and IMD) are of value in signal process-
ing applications.
3. EASE OF USE: The pinout is designed for easy board layout,
and the two-read output provides compatibility with 8-bit
buses. Factory trimming eliminates the need for calibration
modes or external trimming to achieve rated performance.
4. RELIABILITY: The AD679 utilizes Analog Devices’ mono-
lithic BiMOS technology. This ensures long-term reliability
compared to multichip and hybrid designs.
5. UPGRADE PATH: The AD679 provides the same pinout as
the 12-bit, 200 kSPS AD678 ADC.
6. The AD679 is available in versions compliant with MIL-
STD-883. Refer to the Analog Devices Military Products
Databook or current AD679/883B data sheet for detailed
specifications.
REV. D
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2004 Analog Devices, Inc. All rights reserved.
1 page  
ABSOLUTE MAXIMUM RATINGS1
Specification
With
Respect
To
Min
VCC
VEE
VCC2
VDD
AGND
AIN, REFIN
Digital Inputs
Digital Outputs
Max Junction
Temperature
AGND
AGND
VEE
DGND
DGND
AGND
DGND
DGND
–0.3
–18
–0.3
0
–1
VEE
–0.5
–0.5
Max
Unit
+18 V
+0.3 V
+26.4 V
+7 V
+1 V
VCC
V
+7 V
VDD + 0.3 V
175 °C
AD679
Specification
With
Respect
To Min
Max
Unit
Operating
Temperature
J and K Grades
A and B Grades
S and T Grades
Storage Temperature
Lead Temperature
(10 sec max)
0 70
–40 +85
–55 +125
–65 +150
300
°C
°C
°C
°C
°C
NOTES
1Stresses above those listed under Absolute Maximum Ratings may cause perma-
nent damage to the device. This is a stress rating only and functional operation of
the device at these or any other conditions above those indicated in the operational
sections of this specification is not implied. Exposure to absolute maximum rating
conditions for extended periods may affect device reliability.
2The AD679 is not designed to operate from Ϯ15 V supplies.
Model
Package
ORDERING GUIDE1
Temperature
Range
Tested and Package
Specified Option2
AD679JN
AD679KN
AD679JD
AD679KD
AD679AD
AD679BD
AD679SD
AD679TD
AD679AJ
AD679BJ
AD679SD/883B3
28-Pin Plastic DIP
28-Pin Plastic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
28-Pin Ceramic DIP
44-Lead Ceramic JLCC
44-Lead Ceramic JLCC
0°C to +70°C
0°C to +70°C
0°C to +70°C
0°C to +70°C
–40°C to +85°C
–40°C to +85°C
–55°C to +125°C
–55°C to +125°C
–40°C to +85°C
–40°C to +85°C
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
AC + DC
AC
AC + DC
N-28
N-28
D-28
D-28
D-28
D-28
D-28
D-28
J-44
J-44
NOTES
1For parallel read (14-bits) interface to 16-bit buses, see AD779.
2N = Plastic DIP; D = Ceramic DIP; J = J-Leaded Ceramic Chip Carrier.
3For details, grade, and package offerings screened in accordance with MIL-STD-883, refer to the
Analog Devices Military Products Databook or the current AD679/883B data sheet.
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although the
AD679 features proprietary ESD protection circuitry, permanent damage may occur on devices
subjected to high energy electrostatic discharges. Therefore, proper ESD precautions are recommended
to avoid performance degradation or loss of functionality.
REV. D
–5–
5 Page 
AD679
and digital ground planes are also desirable, with a single inter-
connection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
The AD679 incorporates several features to help the user’s lay-
out. Analog pins (VEE, AIN, AGND, REFOUT, REFIN, BIPOFF,
VCC) are adjacent to help isolate analog from digital signals. In
addition, the 10 MΩ input impedance of AIN minimizes input
trace impedance errors. Finally, ground currents have been
minimized by careful circuit architecture. Current through
AGND is 200 µA, with no code dependent variation. The cur-
rent through DGND is dominated by the return current for
DB7–DB0 and EOC.
Figure 7 shows the use of the AD586 with the AD679 in a bipolar
input mode. Over the 0°C to 70°C range, the AD586 L-grade
exhibits less than a 2.25 mV output change from its initial value
at 25°C. REFIN (Pin 9) scales its input by a factor of two; thus,
this change becomes effectively 4.5 mV. When applied to the
AD679, this results in a total gain drift of 0.09% FSR, which is
an improvement over the on-chip reference performance of
0.11% FSR. A noise-reduction capacitor, CN, has been shown.
This capacitor reduces the broadband noise of the AD586 out-
put, thereby optimizing the overall ac and dc performance of the
AD679.
SUPPLY DECOUPLING
The AD679 power supplies should be well filtered, well regu-
lated, and free from high frequency noise. Switching power sup-
plies are not recommended due to their tendency to generate
spikes that can induce noise in the analog system.
Decoupling capacitors should be used in very close layout prox-
imity between all power supply pins and analog ground. A 10 µF
tantalum capacitor in parallel with a 0.1 µF ceramic capacitor
provides adequate decoupling.
An effort should be made to minimize the trace length between
the capacitor leads and the respective converter power supply
and common pins. The circuit layout should attempt to locate
the AD679, associated analog input circuitry, and interconnec-
tions as far as possible from logic circuitry. A solid analog
ground plane around the AD679 isolates large switching ground
currents. For these reasons, the use of wire wrap circuit con-
struction is not recommended; careful printed circuit construc-
tion is preferred.
GROUNDING
If a single AD679 is used with separate analog and digital
ground planes, connect the analog ground plane to AGND and
the digital ground plane to DGND, keeping lead lengths as
short as possible. Then connect AGND and DGND together at
the AD679. If multiple AD679s are used or if the AD679 shares
analog supplies with other components, connect the analog and
digital returns together once at the power supplies rather than at
each chip. This prevents large ground loops, which inductively
couple noise and allow digital currents to flow through the ana-
log system.
USE OF EXTERNAL VOLTAGE REFERENCE
The AD679 features an on-chip voltage reference. For improved
gain accuracy over temperature, a high performance external
voltage reference may be used in place of the on-chip reference.
The AD586 and AD588 are popular references appropriate for
use with high resolution converters. The AD586 is a low cost
reference that utilizes a buried Zener architecture to provide low
noise and drift. The AD588 is a higher performance reference
that uses a proprietary implanted buried Zener diode in con-
junction with laser-trimmed thin-film resistors for low offset and
low drift.
Figure 7. Bipolar Input with Gain and Offset Trims
Figure 8 shows the AD679 in unipolar input mode with the
AD588 reference. The AD588 output is accurate to 0.65 mV
from its value at 25°C over the 0°C to 70°C range. This results
in a 0.06% FSR total gain drift for the AD679, a substantial im-
provement over the on-chip reference performance of 0.11%
FSR. A noise-reduction network on Pins 4, 6, and 7 has been
shown. The 1 µF capacitors form low-pass filters with the inter-
nal resistance of the AD588 Zener and amplifier cells and exter-
nal resistance. This reduces the high frequency (to 1 MHz)
noise of the AD588, providing optimum ac and dc performance
of the AD679.
REFIN
Figure 8. Unipolar Input with Gain and Offset Trims
REV. D
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD679.PDF ] | |
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