|
|
PDF AD6630 Data sheet ( Hoja de datos )
| Número de pieza | AD6630 | |
| Descripción | Differential/ Low Noise IF Gain Block with Output Clamping | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD6630 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
|
No Preview Available !
a
FEATURES
24 dB Gain
4 dB Noise Figure
Easy Match to SAW Filters
Output Limiter Adjustable +8.5 dBm to +12 dBm
700 MHz Bandwidth
10 V Single or Dual 5 V Power Supply
300 mW Power Dissipation
APPLICATIONS
ADC IF Drive Amp
Communications Receivers
PCS/Cellular Base Stations
GSM, CDMA, TDMA
Differential, Low Noise IF Gain
Block with Output Clamping
AD6630
FUNCTIONAL BLOCK DIAGRAM
NC 1
NC 2
IP2 3
IP1 4
IP1 5
IP2 6
CLLO 7
CLHI 8
AD6630
+
+
+
16 VCC
15 CD1
14 OP
13 VEE
12 CMD
11 OP
10 CD2
9 VCC
NC = NO CONNECT
PRODUCT DESCRIPTION
The AD6630 is an IF gain block designed to interface between
SAW filters and differential input analog-to-digital converters.
The AD6630 has a fixed gain of 24 dB and has been optimized
for use with the AD6600 and AD6620 in digitizing narrowband
IF carriers in the 70 MHz to 250 MHz range.
Taking advantage of the differential nature of SAW filters, the
AD6630 has been designed as a differential in/differential out
gain block. This architecture allows 100 dB of adjacent channel
blocking using low cost SAW filters. The AD6630 provides
output limiting for ADC and SAW protection with Ͻ10° phase
variation in recovery from overdrive situations.
Designed for “narrow-band” cellular/PCS receivers, the high
linearity and low noise performance of the AD6630 allows for
implementation in a wide range of applications ranging from
GSM to CDMA to AMPS. The clamping circuitry also main-
tains the phase integrity of an overdriven signal. This allows
phase demodulation of single carrier signals with an overrange
signal.
While the AD6630 is optimized for use with the AD6600 Dual
Channel, Gain Ranging ADC with RSSI, it can also be used in
many other IF applications. The AD6630 is designed with an
input impedance of 200 Ω and an output of 400 Ω. In the typi-
cal application shown below, these values match the real portion
of a typical SAW filter. Other devices can be matched using
standard matching network techniques.
The AD6630 is built using Analog Devices’ high speed comple-
mentary bipolar process. Units are available in a 300 mil SOIC
(16 leads) plastic surface mount package and specified to operate
over the industrial temperature range (–40°C to +85°C).
LOCAL
OSCILLATOR
AD6630
AD6630
MAIN
AD6600 AD6620 DSP
DIVERSITY
Figure 1. Reference Design
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD6630
–1dB 15dB –9dB –2dB 15dB –5dB 24dB –5dB
–28dBm –29dBm –14dBm
LOCAL
OSCILLATOR
–23dBm–25dBm–10dBm–15dBm 9dBm
AD6630
4dBm
MAIN
AD6600
SAW
SAW
DIVERSITY
AD6620
DSP
ANTENNA
–104dBm
–43dBm
–28dBm
–16dBm
–15dBm
AD6630 INPUT
–91dBm
–30dBm
–15dBm
–3dBm
–2dBm
AD6630 OUTPUT
–67dBm
–6dBm
+9dBm
+9dBm
+9dBm
AD6600 INPUT
–71dBm
–10dBm
+4dBm
+4dBm
+4dBm
Figure 6. GSM Design Example
THEORY OF OPERATION
The AD6630 amplifier consists of two stages of gain. The first
stage is differential. This differential amplifier provides good
common-mode rejection to common-mode signals passed by
the SAW filter. The second stage consists of matched current
feedback amplifiers on each side of the differential pair. These
amplifiers provide additional gain as well as output drive capa-
bility. Gain set resistors for these stages are internal to the de-
vice and cannot be changed, allowing fixed compensation for
optimum performance.
Clamping levels for the device are normally set by tying CLLO
or CLHI pins to the negative supply. This internally sets bias
points that generate symmetric clamping levels. Clamping is
achieved primarily in the output amplifiers. Additional input
stage clamping is provided for additional protection. Clamping
levels may be adjusted to lower levels as discussed below.
APPLICATIONS
The AD6630 provides several useful features to meet the needs
of radio designers. The gain and low noise figure of the device
make it perfect for providing interstage gain between differential
SAW filters and/or analog-to-digital converters (ADC). Addi-
tionally, the on-board clamping circuitry provides protection for
sensitive SAW filters or ADCs. The fast recovery of the clamp
circuit permits demodulation of constant envelope modulated
IF signals by preserving the phase response during clamping.
The following topics provide recommendations for using the
AD6630 in narrowband, single carrier applications.
Adjusting Output Clamp Levels
Normally, the output clamp level is set by tying either CLLO or
CLHI to ground or VEE. It is possible to set the limit between
8.5 dBm and 12 dBm levels by selecting the appropriate exter-
nal resistor.
To set to a different level, CLLO and CLHI should be tied
together and then through a resistor to ground. The value of the
resistor can be selected using the following equation.
R =14.4 – OUTPUTCLAMP (dBm)
0.0014
This equation is derived from measured data at 170 MHz. Clamp
levels vary with frequency, see Figure 5. Output clamp levels
less than 8.5 dBm will result in damage to the clamp circuitry
unless the absolute maximum input power is derated. Similarly,
the output clamp level cannot be set higher than 12 dBm.
R
VEE
CLAMP
GENERATOR
Figure 7. Clamp Level Resistor
Matching SAW Filters
The AD6630 is designed to easily match to SAW filters. SAW
filters are largely capacitive in nature. Normally a conjugate
match to the load is desired for maximum power transfer.
Another way to treat the problem is to make the SAW filter look
purely resistive. If the SAW filter load looks resistive there is no
lead or lag in the current vs. voltage. This may not preserve
maximum power transfer, but maximum voltage swing will
exist. All that is required to make the SAW filter input or output
look real is a single inductor shunted across the input. When the
correct value is used, the impedance of the SAW filter becomes
real.
400⍀ 3pF
47nH
9.7⍀
15.2pF
Figure 8. Saw Filter Model (170 MHz)
EVALUATION BOARD
Figures 9, 10 and 12 refer to the schematic and layout of the
AD6630AR as used on Analog Devices’ GSM Diversity Re-
ceiver Reference Design (only the IF section is shown). Figure
14 references the schematic of the stand-alone AD6630 evalua-
tion board and uses a similar layout. The evaluation board uses
center tapped transformers to convert the input to a differential
signal and AD6630 outputs to a single connector to simplify
evaluation. C8, C9 and L2 are optional reactive components to
tune the load for a particular IF frequency if desired.
REV. 0
–5–
5 Page | ||
| Páginas | Total 8 Páginas | |
| PDF Descargar | [ Datasheet AD6630.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD6630 | Differential/ Low Noise IF Gain Block with Output Clamping | Analog Devices |
| AD6633 | Multichannel Digital Upconverter | Analog Devices |
| AD6634 | 80 MSPS/ Dual-Channel WCDMA Receive Signal Processor (RSP) | Analog Devices |
| AD6635 | 4-Channel/ 80 MSPS WCDMA Receive Signal Processor (RSP) | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |