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PDF AD8024 Data sheet ( Hoja de datos )
| Número de pieza | AD8024 | |
| Descripción | Quad 350MHz 24V Amplifier | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8024 (archivo pdf) en la parte inferior de esta página. Total 13 Páginas | ||
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a
Quad 350 MHz
24 V Amplifier
AD8024
FEATURES
Quad High-Speed Current Feedback Amplifier
with Disable
–3 dB Bandwidth 350 MHz @ G = +1
Slew Rate 2400 V/s, VS = ؎12 V
Drives High Capacitive Loads
Settling Time to 0.1% in 35 ns; 300 pF Load, 6 V Step
Settling Time to 0.1% in 18 ns; 5 pF Load, 2 V Step
Low Power
Operates on +5 V to ؎12 V (24 V)
4 mA/Amplifier Supply Current
Excellent Video Specs (RL = 150 ⍀, G = +2)
Gain Flatness 0.1 dB to 70 MHz
0.04% Differential Gain
0.09؇ Differential Phase
Crosstalk –58 dB @ 5 MHz
THD –72 dBc @ 5 MHz
Outstanding DC Accuracy
VOFFSET is 2 mV (Typ)
IBIAS is 3 A (Max)
16-Lead SOIC Package
APPLICATIONS
LCD Column Drivers
High-Performance Test Equipment
Video Line Driver
ATE
PRODUCT DESCRIPTION
The AD8024 is a low settling time, high-speed, high output
voltage quad current feedback operational amplifier. Manu-
factured on ADI’s proprietary XFHV high-speed bipolar process,
the AD8024 is capable of driving to within 1.3 V of its 24 V
supply rail. Each amplifier has high-output current capability
and can drive high capacitive loads.
The AD8024 outputs settle to 0.1% within 35 ns into a 300 pF
load (6 V swing). The AD8024 can run on both 5 V as well as
± 12 V rails. Slew rate on ± 12 V supplies is 2400 V/µs. DC
Characteristics are outstanding with typical 2 mV offset, and
3 µA maximum input bias current. High-speed disable pin
allows the AD8024 to be shut down when not in use. Low-power
operation is assured with the 4 mA/Amplifier supply current draw.
The high voltage drive capability, low settling time, high slew
rate, low offset, and high bandwidth make the AD8024 ideally
suited as an LCD column driver, a video line driver, and for
use in high-performance test equipment.
The AD8024 is available in a 16-lead SOIC package.
FUNCTIONAL BLOCK DIAGRAM
OUT A 1
–IN A 2
+IN A 3
VCC 4
DIS 5
+IN B 6
–IN B 7
OUT B 8
AD8024AR
16 OUT D
15 –IN D
14 +IN D
13 VEE
12 DGND
11 +IN C
10 –IN C
9 OUT C
1V
VIN
20ns
VOUT
2V
Figure 1. Pulse Response Driving a Large Load Capaci-
tance, CL = 300 pF, G = +3, RFB = 2.32 kΩ, RS = 10.5 Ω,
RL = 1 kΩ, VS = ±7.5 V
REV. C
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2001
1 page  
AD8024–Typical Performance Characteristics
12
TA = 25؇C
10
8
6
4
2
–VCM
+VCM
25
TA = 25؇C
20
15
10
5
0
2 4 6 8 10 12
SUPPLY VOLTAGE – ؎Volts
TPC 1. Input Common-Mode Voltage Range vs.
Supply Voltage
0
0 2 4 6 8 10 12 14
SUPPLY VOLTAGE – ؎Volts
TPC 4. Total Supply Current vs. Supply Voltage
7.0
VS = ؎7.5V
6.5
6.0
–SWING
+SWING
5.5
5.0
4.5
4.0
3.5
3.0
10
100 1k
LOAD RESISTANCE – ⍀
10k
TPC 2. Output Voltage Swing vs. Load Resistance
24
22
20
VS = ؎12V
18
16
VS = ؎7.5V
14
12
10
–60 –40 –20 0 20 40 60
TEMPERATURE – ؇C
80 100
TPC 5. Total Supply Current vs. Temperature
25
TA = 25؇C
20
15
SWING
(NO LOAD)
SWING
(RL = 150⍀)
10
5
0
23 45
6 7 8 9 10 11 12 13
SUPPLY VOLTAGE – ؎Volts
TPC 3. Output Voltage Swing vs. Supply Voltage
3
VS = ؎7.5V
2
–IB
1
+IB
0
–1
–60 –40 –20 0 20 40 60
TEMPERATURE – ؇C
80 100
TPC 6. Input Bias Current vs. Temperature
–4– REV. C
5 Page 
AD8024
Overload Recovery
The most important overload conditions are:
Input Common-Mode Voltage Overdrive
Output Voltage Overdrive
Input Current Overdrive.
When configured for a low closed-loop gain, the AD8024
recovers quickly from an input common-mode voltage over-
drive; typically in <25 ns.
When configured for a higher gain and overloaded at the output,
recovery from an output voltage overdrive is also short; approxi-
mately 55 ns (see Figure 5). For higher overdrive, the response
is somewhat slower. For 100% overdrive, the recovery time is
substantially longer.
When configured for a high noninverting gain, a high input over-
drive can result in a large current into the input stage. Although
this current is internally limited to approximately 30 mA, its
effect on the total power dissipation may be significant. See also
the warning under Maximum Power Dissipation.
Disable Mode Operation
When the Disable pin is tied to DGND, all amplifiers are opera-
tional, in the enabled state.
When the voltage on the Disable pin is raised to 1.6 V or more
above DGND, all amplifiers are in the disabled, powered-down
state. In this condition, the DISABLE pin sources approximately
0.1 µA, the total quiescent current is reduced to approximately
500 µA, all outputs are in a high impedance state, and there is a
high level of isolation from inputs to outputs.
The output impedance in the disabled mode is the equivalent of all
external resistors, seen from the output pin, in parallel with the
total disabled output impedance of the amplifier, typically 20 pF.
The input stages of the AD8024 include protection from large
differential input voltages that may be present in the disabled
mode. Internal clamps limit this voltage to 1.5 V. The high input-
to-output isolation is maintained for voltages below this limit.
1V
VIN
50ns
VOUT
5V
Figure 5. 15% Overload Recovery, Gain = +10
(RFB = 400 Ω, RL = 1 kΩ, VS = ±7.5 V)
–10–
REV. C
11 Page | ||
| Páginas | Total 13 Páginas | |
| PDF Descargar | [ Datasheet AD8024.PDF ] | |
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