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PDF AD7945 Data sheet ( Hoja de datos )
| Número de pieza | AD7945 | |
| Descripción | +3.3 V/+5 V Multiplying 12-Bit DACs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7945 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
12-Bit Multiplying DACs
Guaranteed Specifications with +3.3 V/+5 V Supply
0.5 LSBs INL and DNL
Low Power: 5 W typ
Fast Interface
40 ns Strobe Pulsewidth (AD7943)
40 ns Write Pulsewidth (AD7945, AD7948)
Low Glitch: 60 nV-s with Amplifier Connected
Fast Settling: 600 ns to 0.01% with AD843
APPLICATIONS
Battery-Powered Instrumentation
Laptop Computers
Upgrades for All 754x Series DACs (5 V Designs)
GENERAL DESCRIPTION
The AD7943, AD7945 and AD7948 are fast 12-bit multiplying
DACs that operate from a single +5 V supply (Normal Mode)
and a single +3.3 V to +5 V supply (Biased Mode). The
AD7943 has a serial interface, the AD7945 has a 12-bit parallel
interface, and the AD7948 has an 8-bit byte interface. They will
replace the industry-standard AD7543, AD7545 and AD7548
in many applications, and they offer superior speed and power
consumption performance.
The AD7943 is available in 16-lead DIP, 16-lead SOP (Small
Outline Package) and 20-lead SSOP (Shrink Small Outline
Package).
The AD7945 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
The AD7948 is available in 20-lead DIP, 20-lead SOP and 20-
lead SSOP.
+3.3 V/+5 V Multiplying
12-Bit DACs
AD7943/AD7945/AD7948
FUNCTIONAL BLOCK DIAGRAMS
VREF
AD7943
VDD
CLR
LD1
LD2
RFB
12-BIT DAC
DAC REGISTER
IOUT1
IOUT2
AGND
SRI
INPUT SHIFT REGISTER
SRO
VREF
CS
WR
STB1 STB2 STB3 STB4 DGND
VDD
RFB
AD7945
12-BIT DAC
12
IOUT1
AGND
INPUT LATCH
12
DB11–DB0
DGND
VDD
RFB
VREF
12-BIT DAC
12
DATA OVERRIDE LOGIC
12
DAC REGISTER
12
INPUT REGISTERS
12
DATA STEERING LOGIC
8
DB7–DB0
AD7948
CONTROL
LOGIC
IOUT1
AGND
DF/DOR
CTRL
LDAC
WR
CSLSB
CSMSB
DGND
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD7943/AD7945/AD7948
AD7943 TIMING SPECIFICATIONS1 (TA = TMIN to TMAX, unless otherwise noted)
Parameter
tSTB2
tDS
tDH
tSRI
tLD
tCLR
tASB
tSV3
Limit @
VDD = +3 V to +3.6 V
60
15
35
55
55
55
0
60
Limit @
VDD = +4.5 V to +5.5 V
40
10
25
35
35
35
0
35
Units
ns min
ns min
ns min
ns min
ns min
ns min
ns min
ns max
Description
STB Pulsewidth
Data Setup Time
Data Hold Time
SRI Data Pulsewidth
Load Pulsewidth
CLR Pulsewidth
Min Time Between Strobing Input Shift
Register and Loading DAC Register
STB Clocking Edge to SRO Data Valid Delay
NOTES
1All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V. tr and tf should not exceed 1 µs on any digital input.
2STB mark/space ratio range is 60/40 to 40/60.
3tSV is measured with the load circuit of Figure 2 and defined as the time required for the output to cross 0.8 V or 2.4 V.
Specifications subject to change without notice.
STB1,
STB2,
STB4
tSTB
STB3
SRI
tDH
t DS
tSRI
DB11(N)
(MSB)
LD1,
LD2,
CLR
SRO
DB10(N)
t SV
DB10(N–1)
Figure 1. AD7943 Timing Diagram
DB0(N)
tASB
tLD, tCLR
DB0(N–1)
1.6mA IOL
TO OUTPUT
PIN
CL
50pF
200A IOH
+2.1V
Figure 2. Load Circuit for Digital Output Timing Specifications
REV. B
–5–
5 Page 
Typical Performance Curves
0.5
VDD = +5V
TA = +25؇C
0.4 OP AMP = AD843
0.3
0.2
0.1
0
2 4 6 8 10
VREF – Volts
Figure 5. Differential Nonlinearity Error vs.
VREF (Normal Mode)
1.0
VDD = +5V
0.9 TA = +25؇C
OP AMP = AD843
0.8
0.7
0.6
0.5
0.4
0.3
0.2
0.1
0
24
6 8 10
VREF – Volts
Figure 6. Integral Nonlinearity Error vs.
VREF (Normal Mode)
AD7943/AD7945/AD7948
0.50
0.25
VDD = +5V
VREF = +10V
OP AMP = AD843
TA = +25؇C
0.00
–0.25
–0.50
0
1024
2048
INPUT CODE
3072
4095
Figure 7. All Codes Linearity In Normal Mode (VDD = +5 V)
6
VDD = +3.3V
5 TA = +25؇C
OP AMP = AD820
4
3
2
1
0
0.2 0.4
0.6 0.8 1.0
|VREF – VBIAS| – Volts
1.2 1.4
Figure 8. Linearity Error vs. VREF (Biased Mode)
REV. B
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7945.PDF ] | |
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