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PDF AD7895 Data sheet ( Hoja de datos )
| Número de pieza | AD7895 | |
| Descripción | 5 V/ 12-Bit/ Serial 3.8 ms ADC in 8-Pin Package | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Fast 12-Bit ADC with 3.8 s Conversion Time
8-Pin Mini-DlP and SOIC
Single 5 V Supply Operation
High Speed, Easy-to-Use, Serial Interface
On-Chip Track/Hold Amplifier
Selection of Input Ranges
؎10 V for AD7895-10
؎2.5 V for AD7895-3
0 V to +2.5 V for AD7895-2
High Input Impedance
Low Power: 20 mW max
14-Bit Pin Compatible Upgrade (AD7894)
5 V, 12-Bit, Serial 3.8 s
ADC in 8-Pin Package
AD7895
FUNCTIONAL BLOCK DIAGRAM
AD7895
REF IN
VDD
TRACK/HOLD
VIN
SIGNAL
SCALING*
12-BIT
ADC
CONVST
OUTPUT
REGISTER
GENERAL DESCRIPTION
The AD7895 is a fast 12-bit ADC that operates from a single
+5 V supply and is housed in a small 8-pin mini-DIP and 8-pin
SOIC. The part contains a 3.8 µs successive approximation A/D
converter, an on-chip track/hold amplifier, an on-chip clock and
a high speed serial interface.
Output data from the AD7895 is provided via a high speed,
serial interface port. This two-wire serial interface has a serial
clock input and a serial data output with the external serial clock
accessing the serial data from the part.
In addition to the traditional dc accuracy specifications such as
linearity and full-scale and offset errors, the AD7895 is specified
for dynamic performance parameters, including harmonic
distortion and signal-to-noise ratio.
The part accepts an analog input range of ± 10 V (AD7895-10),
± 2.5 V (AD7895-3), 0 V to 2.5 V (AD7895-2) and operates
from a single +5 V supply, consuming only 20 mW max.
The AD7895 features a high sampling rate mode and, for low
power applications, a proprietary automatic power-down mode
where the part automatically goes into power down once
conversion is complete and “wakes up” before the next conver-
sion cycle.
The part is available in a small, 8-pin, 0.3" wide, plastic dual-in-
line package (mini-DIP) and in an 8-pin, small outline IC (SOIC).
GND
BUSY
*AD7895-10, AD7895-3
SCLK SDATA
PRODUCT HIGHLIGHTS
1. Fast, 12-Bit ADC in 8-Pin Package
The AD7895 contains a 3.8 µs ADC, a track/hold amplifier,
control logic and a high speed serial interface, all in an 8-pin
package. This offers considerable space saving over alterna-
tive solutions.
2. Low Power, Single Supply Operation
The AD7895 operates from a single +5 V supply and
consumes only 20 mW. The automatic power-down mode,
where the part goes into power-down once conversion is
complete and “wakes up” before the next conversion cycle,
makes the AD7895 ideal for battery-powered or portable
applications.
3. High Speed Serial Interface
The part provides high speed serial data and serial clock lines
allowing for an easy, two-wire serial interface arrangement.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
AD7895
TERMINOLOGY
Signal to (Noise + Distortion) Ratio
This is the measured ratio of signal to (noise + distortion) at the
output of the A/D converter. The signal is the rms amplitude of
the fundamental. Noise is the rms sum of all nonfundamental
signals up to half the sampling frequency (fS/2), excluding dc.
The ratio is dependent upon the number of quantization levels
in the digitization process; the more levels, the smaller the
quantization noise. The theoretical signal to (noise + distortion)
ratio for an ideal N-bit converter with a sine wave input is given
by:
Signal to (Noise + Distortion) = (6.02 N + 1.76) dB
Thus for a 12-bit converter, this is 74 dB.
Total Harmonic Distortion
Total harmonic distortion (THD) is the ratio of the rms sum of
harmonics to the fundamental. For the AD7895, it is defined as:
THD (dB) = 20 log
V
2
2
+V
2
3
+V
2
4
+V
2
5
+V
2
6
V1
where V1 is the rms amplitude of the fundamental, and V2, V3,
V4, V5 and V6 are the rms amplitudes of the second through the
sixth harmonics.
Peak Harmonic or Spurious Noise
Peak harmonic or spurious noise is defined as the ratio of the
rms value of the next largest component in the ADC output
spectrum (up to fS/2 and excluding dc) to the rms value of the
fundamental. Normally, the value of this specification is
determined by the largest harmonic in the spectrum, but for
parts where the harmonics are buried in the noise floor, it will
be a noise peak.
Intermodulation Distortion
With inputs consisting of sine waves at two frequencies, fa and
fb, any active device with nonlinearities will create distortion
products at sum and difference frequencies of mfa ± nfb where
m, n = 0, 1, 2, 3, etc. Intermodulation terms are those for which
neither m or n are equal to zero. For example, the second order
terms include (fa + fb) and (fa – fb), while the third order terms
include (2 fa + fb), (2 fa – fb), (fa + 2 fb) and (fa – 2 fb).
The AD7895 is tested using the CCIF standard where two
input frequencies near the top end of the input bandwidth are
used. In this case, the second and third order terms are of
different significance. The second order terms are usually
distanced in frequency from the original sine waves, while the
third order terms are usually at a frequency close to the input
frequencies. As a result, the second and third order terms are
specified separately. The calculation of the intermodulation
distortion is as per the THD specification where it is the ratio of
the rms sum of the individual distortion products to the rms
amplitude of the fundamental expressed in dBs.
Relative Accuracy
Relative accuracy or endpoint nonlinearity is the maximum
deviation from a straight line passing through the endpoints of
the ADC transfer function.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Positive Full-Scale Error (AD7895-10)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal (4 × VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7895-3)
This is the deviation of the last code transition (01 . . . 110 to
01 . . . 111) from the ideal ( VREF – 1 LSB) after the
Bipolar Zero Error has been adjusted out.
Positive Full-Scale Error (AD7895-2)
This is the deviation of the last code transition (11 . . . 110 to
11 . . . 111) from the ideal (VREF – 1 LSB) after the Unipolar
Offset Error has been adjusted out.
Bipolar Zero Error (AD7895-10, AD7895-3)
This is the deviation of the midscale transition (all 0s to all 1s)
from the ideal 0 V (GND).
Unipolar Offset Error (AD7895-2)
This is the deviation of the first code transition (00 . . . 000 to
00 . . . 001) from the ideal 1 LSB.
Negative Full-Scale Error (AD7895-10)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–4 × VREF + 1 LSB) after Bipolar
Zero Error has been adjusted out.
Negative Full-Scale Error (AD7895-3)
This is the deviation of the first code transition (10 . . . 000 to
10 . . . 001) from the ideal (–VREF + 1 LSB) after Bipolar Zero
Error has been adjusted out.
Track/Hold Acquisition Time
Track/Hold acquisition time is the time required for the output
of the track/hold amplifier to reach its final value, within
± 1/2 LSB, after the end of conversion (the point at which the
track/hold returns to track mode). It also applies to situations
where there is a step input change on the input voltage applied
to the VIN input of the AD7895. This means that the user must
wait for the duration of the track/hold acquisition time after the
end of conversion or after a step input change to VIN before
starting another conversion to ensure that the part operates to
specification.
REV. 0
–5–
5 Page 
Dynamic Performance (Mode 1 Only)
With a combined conversion and acquisition time of 4.1 µs, the
AD7895 is ideal for wide bandwidth signal processing applica-
tions. These applications require information on the ADC’s
effect on the spectral content of the input signal. Signal to
(Noise + Distortion), Total Harmonic Distortion, Peak Har-
monic or Spurious Noise, and Intermodulation Distortion are
all specified. Figure 11 shows a typical FFT plot of a 10 kHz,
0 V to +5 V input after being digitized by the AD7895 operating
at a 198.656 kHz sampling rate. The Signal to (Noise + Distor-
tion) Ratio is 73.04 dB, and the Total Harmonic Distortion is
–84.91 dB.
The formula for Signal to (Noise + Distortion) Ratio (see
Terminology section) is related to the resolution or number of
bits in the converter. Rewriting the formula, below, gives a
measure of performance expressed in effective number of bits (N):
N = (SNR 1.76)/6.02
where SNR is Signal to (Noise + Distortion) Ratio.
–0
–10 FSAMPLE = 198656
FIN = 10kHz
–20 SNR = –73.04dB
THD = –84.91dB
–30
–40
–50
–60
–70
–80
–90
–100
–110
–120
0 10k 30k 50k 70k 90k 9.9k
Figure 11. AD7896 FFT Plot Effective Number of Bits
The effective number of bits for a device can be calculated from
its measured Signal to (Noise + Distortion) Ratio. Figure 12
shows a typical plot of effective number of bits versus frequency
for the AD7895 from dc to fSAMPLING/2. The sampling frequency
is 198.656 kHz. The plot shows that the AD7895 converts an
input sine wave of 10 kHz to an effective numbers of bits of
11.84, which equates to a Signal to (Noise + Distortion) level of
73.04 dB.
AD7895
12.0
11.8
11.6
11.4
11.2
11.0
10.8
10.6
10.4
10.2
10.0
0
200 400 600 800
FREQUENCY – kHz
1000
Figure 12. Effective Number of Bits vs. Frequency
Power Considerations
In the automatic power-down mode, then, the part may be
operated at a sample rate that is considerably less than
100 kHz. In this case, the power consumption will be reduced
and will depend on the sample rate. Figure 13 shows a graph
of the power consumption versus sampling rates from 100 Hz to
90 kHz in the automatic power-down mode. The conditions
are 5 V supply 25°C, serial clock frequency of 8.33 MHz, and
the data was read after conversion.
11
10
9
8
7
6
5
4
3
2
1
0
0.1 10 20 30 40 50 60 70 80 90
FREQUENCY – kHz
Figure 13. Power vs. Sample Rate in Auto Power-Down
Mode
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7895.PDF ] | |
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