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PDF AD7853L Data sheet ( Hoja de datos )
| Número de pieza | AD7853L | |
| Descripción | 3 V to 5 V Single Supply/ 200 kSPS 12-Bit Sampling ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
3 V to 5 V Single Supply, 200 kSPS
12-Bit Sampling ADCs
FEATURES
Specified for VDD of 3 V to 5.5 V
Read-Only Operation
AD7853–200 kSPS; AD7853L–100 kSPS
System and Self-Calibration with Autocalibration on
Power-Up
Low Power:
AD7853: 12 mW (VDD = 3 V)
AD7853L: 4.5 mW (VDD = 3 V)
Automatic Power Down After Conversion (25 W)
Flexible Serial Interface:
8051/SPI™/QSPI™/P Compatible
24-Lead DIP, SOIC and SSOP Packages
APPLICATIONS
Battery-Powered Systems (Personal Digital Assistants,
Medical Instruments, Mobile Communications)
Pen Computers
Instrumentation and Control Systems
High Speed Modems
AIN(+)
AIN(–)
REFIN/
REFOUT
CREF1
CREF2
CAL
AD7853/AD7853L*
FUNCTIONAL BLOCK DIAGRAM
AVDD
AGND AGND
T/H
2.5V
REFERENCE
BUF
AD7853/AD7853L
DVDD
DGND
COMP
CHARGE
REDISTRIBUTION
DAC
CALIBRATION
MEMORY
AND CONTROLLER
SAR + ADC
CONTROL
AMODE
CLKIN
CONVST
BUSY
SLEEP
GENERAL DESCRIPTION
The AD7853/AD7853L are high speed, low power, 12-bit
ADCs that operate from a single 3 V or 5 V power supply, the
AD7853 being optimized for speed and the AD7853L for low
power. The ADC powers up with a set of default conditions at
which time it can be operated as a read-only ADC. The ADC
contains self-calibration and system-calibration options to en-
sure accurate operation over time and temperature and have a
number of power-down options for low power applications.
The part powers up with a set of default conditions and can
operate as a read only ADC.
The AD7853 is capable of 200 kHz throughput rate while the
AD7853L is capable of 100 kHz throughput rate. The input
track-and-hold acquires a signal in 500 ns and features a pseudo-
differential sampling scheme. The AD7853/AD7853L voltage
range is 0 to VREF with both straight binary and twos comple-
ment output coding. Input signal range is to the supply, and the
part is capable of converting full power signals to 100 kHz.
CMOS construction ensures low power dissipation of typically
4.5 mW for normal operation and 1.15 mW in power-down
mode, with a throughput rate of 10 kSPS (VDD = 3 V). The part
is available in 24-lead, 0.3 inch wide dual-in-line package
(DIP), 24-lead small outline (SOIC) and 24-lead small shrink
outline (SSOP) packages.
SERIAL INTERFACE / CONTROL REGISTER
SM1 SM2 SYNC DIN DOUT SCLK POLARITY
PRODUCT HIGHLIGHTS
1. Specified for 3 V and 5 V supplies.
2. Automatic calibration on power-up.
3. Flexible power management options including automatic
power-down after conversion.
4. Operates with reference voltages from 1.2 V to VDD.
5. Analog input ranges from 0 V to VDD.
6. Self- and system calibration.
7. Versatile serial I/O port (SPI/QSPI/8051/µP).
8. Lower power version AD7853L.
*Patent pending.
SPI and QSPI are trademarks of Motorola, Incorporated.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1998
1 page  
AD7853/AD7853L
TYPICAL TIMING DIAGRAMS
Figures 2 and 3 show typical read and write timing diagrams.
Figure 2 shows the reading and writing after conversion in In-
terface Modes 2 and 3. To attain the maximum sample rate of
100 kHz (AD7853L) or 200 kHz (AD7853) in Interface Modes
2 and 3, reading and writing must be performed during conver-
sion. Figure 3 shows the timing diagram for Interface Modes 4
and 5 with sample rate of 100 kHz (AD7853L) or 200 kHz
(AD7853). At least 400 ns acquisition time must be allowed
(the time from the falling edge of BUSY to the next rising edge
of CONVST) before the next conversion begins to ensure that
the part is settled to the 12-bit level. If the user does not want to
provide the CONVST signal, the conversion can be initiated in
software by writing to the control register.
1.6mA IOL
TO OUTPUT
PIN
CL
100pF
+2.1V
200A IOH
Figure 1. Load Circuit for Digital Output Timing
Specifications
POLARITY PIN LOGIC HIGH
t1
tCONVERT = 4.6s MAX, 10s FOR L VERSION
t1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT
SYNC (I/P)
SCLK (I/P)
DOUT (O/P)
t5
THREE-
STATE
t3
1
t6
DB15
t7 t8
t9
56
t10
t6
DB11
t11
16
t12
DB0
THREE-
STATE
DB15
DB11
DB0
Figure 2. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 2, 3)
POLARITY PIN LOGIC HIGH
t1
CONVST (I/P)
t2
BUSY (O/P)
tCONVERT = 4.6s MAX, 10s FOR L VERSION
t1 = 100 ns MIN, t5 = 50/90 ns MAX 5V/3V, t7 = 40/60 ns MIN 5V/3V
tCONVERT
SYNC (O/P)
SCLK (O/P)
t4
1
t5
t9
56
t6 t10
t11
16
t12
DOUT (O/P)
DIN (I/P)
THREE-
STATE
t7
t8
DB15
DB15
DB11
DB11
DB0
DB0
THREE-
STATE
Figure 3. AD7853/AD7853L Timing Diagram (Typical Read and Write Operation for Interface Modes 4, 5)
REV. B
–5–
5 Page 
AD7853/AD7853L
STATUS REGISTER
The arrangement of the status register is shown below. The status register is a read-only register and contains 16 bits of data. The
status register is selected by first writing to the control register and putting two 1s in RDSLT1 and RDSLT0. The function of the
bits in the status register are described below. The power-up status of all bits is 0.
START
WRITE TO CONTROL REGISTER
SETTING RDSLT0 = RDSLT1 = 1
READ STATUS REGISTER
MSB
ZERO
Figure 6. Flowchart for Reading the Status Register
BUSY
ZERO
ZERO
ZERO
ZERO PMGT1 PMGT0
RDSLT1 RDSLT0 2/3 MODE
X
CALMD CALSLT1 CALSLT0
STCAL
LSB
Bit Mnemonic
15 ZERO
14 BUSY
13 ZERO
12 ZERO
11 ZERO
10 ZERO
9 PMGT1
8 PMGT0
7 RDSLT1
6 RDSLT0
5 2/3 MODE
4X
3 CALMD
2 CALSLT1
1 CALSLT0
0 STCAL
Status Register Bit Function Descriptions
Comment
This bit is always 0.
Conversion/Calibration Busy Bit. When this bit is 1, it indicates that there is a conversion or calibration in
progress. When this bit is 0, no conversion or calibration is in progress.
These four bits are always 0.
Power Management Bits. These bits, along with the SLEEP pin, will indicate whether or not the part is in a
power-down mode. See Table VI in Power-Down Section for description.
Both of these bits are always 1, indicating it is the status register that is being read. See Table II.
Interface Mode Select Bit. With this bit at 0, the device is in Interface Mode 2. With this bit at 1, the device
is in Interface Mode 1. This bit is reset to 0 after every read cycle.
Don’t care bit.
Calibration Mode Bit. A 0 in this bit indicates a self-calibration is selected; a 1 in this bit indicates a system
calibration is selected (see Table III).
Calibration Selection Bits and Start Calibration Bit. The STCAL bit is read as a 1 if a calibration is in
progress and as a 0 if no calibration is in progress. The CALSLT1 and CALSLT0 bits indicate
which of the calibration registers are addressed for reading and writing (see section on the Calibration
Registers for more details).
REV. B
–11–
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD7853L.PDF ] | |
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