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PDF AD7843 Data sheet ( Hoja de datos )
| Número de pieza | AD7843 | |
| Descripción | Touch Screen Digitizer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7843 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
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FEATURES
4-Wire Touch Screen Interface
Specified Throughput Rate of 125 kSPS
Low Power Consumption:
1.37 mW Max at 125 kSPS with VCC = 3.6 V
Single Supply, VCC of 2.2 V to 5.25 V
Ratiometric Conversion
High-Speed Serial Interface
Programmable 8- or 12-Bit Resolution
Two Auxiliary Analog Inputs
Shutdown Mode: 1 A max
16-Lead QSOP and TSSOP Packages
APPLICATIONS
Personal Digital Assistants
Smart Hand-Held Devices
Touch Screen Monitors
Point-of-Sales Terminals
Pagers
Touch Screen Digitizer
AD7843
FUNCTIONAL BLOCK DIAGRAM
+VCC
PENIRQ
X+
X–
Y+
Y–
IN3
IN4
VREF
AD7843
PEN
INTERRUPT
4-TO-1
I/P
MUX
T/H
COMP
CHARGE
REDISTRIBUTION
DAC
SAR + ADC
CONTROL LOGIC
GND
+VCC
GENERAL DESCRIPTION
The AD7843 is a 12-bit successive-approximation ADC with a
synchronous serial interface and low on resistance switches for
driving touch screens. The part operates from a single 2.2 V to
5.25 V power supply and features throughput rates greater than
125 kSPS.
The external reference applied to the AD7843 can be varied
from 1 V to +VCC, while the analog input range is from 0 V to
VREF. The device includes a shutdown mode that reduces the
current consumption to less than 1 µA.
The AD7843 features on-board switches. This coupled with low
power and high-speed operation make this device ideal for
battery-powered systems such as personal digital assistants with
resistive touch screens and other portable equipment. The part
is available in a 16-lead 0.15" Quarter Size Outline (QSOP) pack-
age and a 16-lead Thin Shrink Small Outline (TSSOP) package.
SPORT
DIN
CS
DOUT DCLK
BUSY
PRODUCT HIGHLIGHTS
1. Ratiometric conversion mode available eliminating errors
due to on-board switch resistances.
2. Maximum current consumption of 380 µA while operating at
125 kSPS.
3. Power-down options available.
4. Analog input range from 0 V to VREF.
5. Versatile serial I/O port.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Pin
No.
1, 10
2
3
4
5
6
7
8
9
11
12
13
14
15
16
Mnemonic
+VCC
X+
Y+
X–
Y–
GND
IN3
IN4
VREF
PENIRQ
DOUT
BUSY
DIN
CS
DCLK
PIN FUNCTION DESCRIPTIONS
AD7843
Function
Power Supply Input. The +VCC range for the AD7843 is from 2.2 V to 5.25 V. Both +VCC pins should
be connected directly together.
X+ Position Input. ADC Input Channel 1.
Y+ Position Input. ADC Input Channel 2.
X– Position Input.
Y– Position Input.
Analog Ground. Ground reference point for all circuitry on the AD7843. All analog input signals and
any external reference signal should be referred to this GND voltage.
Auxiliary Input 1. ADC Input Channel 3.
Auxiliary Input 2. ADC Input Channel 4.
Reference Input for the AD7843. An external reference must be applied to this input. The voltage
range for the external reference is 1.0 V to +VCC. For specified performance it is 2.5 V.
Pen Interrupt. CMOS Logic open drain output (requires 10 kΩ to 100 kΩ pull-up resistor externally).
Data Out. Logic Output. The conversion result from the AD7843 is provided on this output as a
serial data stream. The bits are clocked out on the falling edge of the DCLK input. This output is
high impedance when CS is high.
BUSY Output. Logic Output. This output is high impedance when CS is high.
Data In. Logic Input. Data to be written to the AD7843’s Control Register is provided on this input
and is clocked into the register on the rising edge of DCLK (see Control Register section).
Chip Select Input. Active Low Logic Input. This input provides the dual function of initiating con-
versions on the AD7843 and also enables the serial input/output register.
External Clock Input. Logic Input. DCLK provides the serial clock for accessing data from the part.
This clock input is also used as the clock source for the AD7843’s conversion process.
TERMINOLOGY
Integral Nonlinearity
This is the maximum deviation from a straight line passing
through the endpoints of the ADC transfer function. The end-
points of the transfer function are zero scale, a point 1 LSB
below the first code transition, and full scale, a point 1 LSB
above the last code transition.
Differential Nonlinearity
This is the difference between the measured and the ideal 1 LSB
change between any two adjacent codes in the ADC.
Offset Error
This is the deviation of the first code transition (00 . . . 000) to
(00 . . . 001) from the ideal, i.e., AGND + 1 LSB.
Gain Error
This is the deviation of the last code transition (111 . . . 110) to
(111 . . . 111) from the ideal (i.e., VREF – 1 LSB) after the offset
error has been adjusted out.
Track/Hold Acquisition Time
The track/hold amplifier enters the acquisition phase on the fifth
falling edge of DCLK after the START bit has been detected.
Three DCLK cycles are allowed for the Track/Hold acquisition
time and the input signal will be fully acquired to the 12-bit
level within this time even with the maximum specified DCLK
frequency. See Analog Input section for more details.
On-Resistance
This is a measure of the ohmic resistance between the drain and
source of the switch drivers.
REV. 0
–5–
5 Page 
AD7843
reference mode can only be used with +VCC as the source of the
+REF voltage and cannot be used with VREF.
The disadvantage of this mode of operation is that during both
the acquisition phase and conversion process, the external touch
screen must remain powered. This will result in additional sup-
ply current for the duration of the conversion.
+VCC
Y+
X+ IN+ REF+
IN+ ADC CORE
IN– REF–
Y–
GND
Figure 7. Differential Reference Mode (SER/DFR = 0)
CONTROL REGISTER
The control word provided to the ADC via the DIN pin is
shown in Table II. This provides the conversion start, channel
addressing, ADC conversion resolution, configuration and
power-down of the AD7843. Table II provides detailed infor-
mation on the order and description of these control bits within
the control word.
Initiate START
The first bit, the “S” bit, must always be set to 1 to initiate the
start of the control word. The AD7843 will ignore any inputs on
the DIN line until the start bit is detected.
Channel Addressing
The next three bits in the control register, A2, A1 and A0, select
the active input channel(s) of the input multiplexer (see Table I
and Figure 4), touch screen drivers, and the reference inputs.
MODE
The MODE bit sets the resolution of the analog to digital con-
verter. With a 0 in this bit the following conversion will have
12 bits of resolution. With a 1 in this bit the following conver-
sion will have 8 bits of resolution.
SER/DFR
The SER/DFR bit controls the reference mode which can be
either single ended or differential if a 1 or a 0 is written to this
bit respectively. The differential mode is also referred to as
the ratiometric conversion mode. This mode is optimum for
X-Position and Y-Position measurements. The reference is
derived from the voltage at the switch drivers, which is almost
the same as the voltage to the touch screen. In this case a sepa-
rate reference voltage is not needed as the reference voltage to
the analog to digital converter is the voltage across the touch
screen. In the single-ended mode, the reference voltage to the
converter is always the difference between the VREF and GND pins.
See Table I and Figures 4 through 7 for further information.
As the supply current required by the device is so low, a preci-
sion reference can be used as the supply source to the AD7843.
It may also be necessary to power the touch screen from the
reference, which may require 5 mA to 10 mA. A REF19x volt-
age reference can source up to 30 mA and, as such, could supply
both the ADC and the touch screen. Care must be taken, how-
ever, to ensure that the input voltage applied to the ADC does
not exceed the reference voltage and hence the supply voltage.
See Maximum Ratings section.
NOTE: The differential mode can only be used for X-Position
and Y-Position measurements All other measurements require
the single-ended mode.
PD0 and PD1
The power management options are selected by programming
the power management bits, PD0 and PD1, in the control regis-
ter. Table III summarizes the available options.
MSB
S
A2
Table II. Control Register Bit Function Description
A1 A0 MODE SER/DFR PD1
LSB
PD0
Bit Mnemonic
7S
6–4 A2–A0
3 MODE
2 SER/DFR
1, 0 PD1, PD0
Comment
Start Bit. The Control word starts with the first high bit on DIN. A new control word can start every fifteenth
DCLK cycle when in the 12-bit conversion mode or every eleventh DCLK cycle when in 8-bit conversion mode.
Channel Select Bits. These three address bits along with the SER/DFR bit control the setting of the multi-
plexer input, switches, and reference inputs, as detailed in Table I.
12-Bit/8-Bit Conversion Select Bit. This bit controls the resolution of the following conversion. With a 0 in
this bit the conversion will have 12-bit resolution or with a 1 in this bit, 8-bit resolution.
Single-Ended/Differential Reference Select Bit. Along with bits A2–A0, this bit controls the setting of the
multiplexer input, switches, and reference inputs as described in Table I.
Power Management Bits. These two bits decode the power-down mode of the AD7843 as shown in Table III.
REV. 0
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7843.PDF ] | |
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