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PDF AD7841 Data sheet ( Hoja de datos )
| Número de pieza | AD7841 | |
| Descripción | Octal 14-Bit/ Parallel Input/ Voltage-Output DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Octal 14-Bit, Parallel Input,
Voltage-Output DAC
AD7841
FEATURES
Eight 14-Bit DACs in One Package
Voltage Outputs
Offset Adjust for Each DAC Pair
Reference Range of ؎5 V
Maximum Output Voltage Range of ؎10 V
؎15 V ؎ 10% Operation
Clear Function to User-Defined Voltage
44-Lead MQFP Package
APPLICATIONS
Automatic Test Equipment
Process Control
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7841 contains eight 14-bit DACs on one monolithic
chip. It has output voltages with a full-scale range of ± 10 V
from reference voltages of ± 5 V.
The AD7841 accepts 14-bit parallel loaded data from the exter-
nal bus into one of the input registers under the control of the
WR, CS and DAC channel address pins, A0–A2.
The DAC outputs are updated on reception of new data into
the DAC registers. All the outputs may be updated simulta-
neously by taking the LDAC input low.
Each DAC output is buffered with a gain-of-two amplifier into
which an external DAC offset voltage can be inserted via the
DUTGNDx pins.
The AD7841 is available in a 44-lead MQFP package.
VCC
VSS VDD
FUNCTIONAL BLOCK DIAGRAM
VREF(+) VREF(–)
AB AB
DUTGND
CD
DUTGND
AB
DB13
DB0
WR
CS
A0
A1
A2
LDAC
AD7841
14 INPUT 14
REG
A
DAC 14
REG
A
DAC A
14 INPUT 14
REG
B
DAC 14
REG
B
DAC B
14 INPUT 14
REG
C
DAC 14
REG
C
DAC C
14 INPUT 14
REG
D
DAC 14
REG
D
DAC D
14 INPUT 14
REG
E
DAC 14
REG
E
DAC E
14 INPUT 14
REG
F
DAC 14
REG
F
DAC F
14 INPUT 14
REG
G
DAC 14
REG
G
DAC G
14 INPUT 14
REG
H
DAC 14
REG
H
DAC H
RR
RR
R
R
RR
VOUTA
VOUTB
VOUTC
VOUTD
VOUTE
RR
VOUTF
RR
VOUTG
RR
VOUTH
RR
REV. 0
GND
VREF(+) VREF(–)
GH GH
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
VREF(+) VREF(–)
CDEF CDEF
CLR DUTGND DUTGND
EF GH
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
AD7841
PIN FUNCTION DESCRIPTIONS
Pin
No. Mnemonic
Description
1 DUTGND_AB
2, 32, 34,
35, 37, 41,
43, 44
3, 4
5, 38
6, 29
7
VOUTA . . VOUTH
VREF(–)AB, VREF(+)AB
VDD
VSS
LDAC
8, 9, 10
11
12
A2, A1, A0
CS
WR
13
14
15–28
29
VCC
GND
DB0␣ .␣ .␣ DB12
CLR
30, 31
33
36
39
40
42
VREF(+)GH, VREF(–)GH
DUTGND_GH
DUTGND_EF
VREF(+)CDEF
VREF(–)CDEF
DUTGND_CD
Device Sense Ground for DACs A and B. VOUTA and VOUTB are referenced to the voltage
applied to this pin.
DAC Outputs.
Reference Inputs for DACs A and B. These reference voltages are referred to GND.
Positive Analog Power Supply; +15 V ± 10% for Special Performance.
Negative Analog Power Supply; –15 V ± 10% for Special Performance.
Load DAC Logic Input (active low). When this logic input is taken low the contents of the
registers are transferred to their respective DAC registers. LDAC can be tied permanently
low enabling the outputs to be updated on the rising edge of WR.
Address inputs. A0, A1 and A2 are decoded to select one of the eight input registers for a
data transfer.
Level-Triggered Chip Select Input (active low). The device is selected when this input is low.
Level-Triggered Write Input (active low), used in conjunction with CS to write data to the
AD7841 data registers. Data is latched into the selected input register on the rising edge
of WR.
Logic Power Supply; +5 V ± 5%.
Ground.
Parallel Data Inputs. The AD7841 can accept a straight 14-bit parallel word on DB0 to
DB13 where DB13 is the MSB and DB0 is the LSB.
Asynchronous Clear Input (level sensitive, active low). When this input is low, all analog
outputs are switched to the externally set potential on the relevant DUTGND pin. The con-
tents of input registers and DAC registers A to H are not affected when the CLR pin is taken
low. When CLR is brought back high, the DAC outputs revert to their original outputs as
determined by the data in their DAC registers.
Reference Inputs for DACs G and H. These reference voltages are referred to GND.
Device Sense Ground for DACs G and H. VOUTG and VOUTH are referenced to the voltage
applied to this pin.
Device Sense Ground for DACs E and F. VOUTE and VOUTF are referenced to the voltage
applied to this pin.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Reference Inputs for DACs C, D, E and F. These reference voltages are referred to GND.
Device Sense Ground for DACs C and D. VOUTC and VOUTD are referenced to the voltage
applied to this pin.
REV. 0
–5–
5 Page 
AD7841
device. Figure 20 shows the recommended capacitor values of
10 µF in parallel with 0.1 µF on each of the supplies. The 10 µF
capacitors are the tantalum bead type. The 0.1 µF capacitor
should have low Effective Series Resistance (ESR) and Effective
Series Inductance (ESI), such as the common ceramic types,
which provide a low impedance path to ground at high frequen-
cies to handle transient currents due to internal logic switching.
0.1F 10F
VCC
VDD
AD7841
10F 0.1F
VSS
10F 0.1F
Figure 20. Recommended Decoupling Scheme for AD7841
Automated Test Equipment
The AD7841 is particularly suited for use in an automated test
environment. Figure 21 shows the AD7841 providing the neces-
sary voltages for the pin driver and the window comparator in a
typical ATE pin electronics configuration. AD588s are used to
provide reference voltages for the AD7841. In the configuration
shown, the AD588s are configured so that the voltage at Pin 1 is
5 V greater than the voltage at Pin 9 and the voltage at Pin 15 is
5 V less than the voltage at Pin 9.
+15V –15V
VOFFSET
2 16
43
61
8 15
13 AD588 14
VREF(+)AB
VREF(–)AB
VOUTA
10
11
9 VOUTB
DUTGND_AB
12 0.1F
7
1F
AD7841*
+15V
PIN
DRIVER
–15V
+15V –15V
2 16
43
61
8 15
13 AD588 14
10
11 9
DUTGND_GH
VOUTG
VREF(+)GH
VREF(–)GH
VOUTH
GND
DEVICE
GND
VOUT
DEVICE
GND
12
7
1F
DEVICE
GND
WINDOW
COMPARATOR
TO TESTER
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. ATE Application
One of the AD588s is used as a reference for DACs A and B.
These DACs are used to provide high and low levels for the pin
driver. The pin driver may have an associated offset. This can
be nulled by applying an offset voltage to Pin 9 of the AD588.
First, the code 1000␣ .␣ .␣ .␣ 0000 is loaded into the DACA latch
and the pin driver output is set to the DACA output. The
VOFFSET voltage is adjusted until 0 V appears between the pin
driver output and DUTGND. This causes both VREF(+) and
VREF(–) to be offset with respect to GND by an amount equal to
VOFFSET. However, the output of the pin driver will vary from
–10 V to +10 V with respect to DUTGND as the DAC input
code varies from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111. The VOFFSET
voltage is also applied to the DUTGND pins. When a clear is
performed on the AD7841, the output of the pin driver will be
0 V with respect to DUTGND.
The other AD588 is used to provide a reference voltage for
DACs G and H. These provide the reference voltages for the
window comparator shown in the diagram. Note that Pin 9 of
this AD588 is connected to Device GND. This causes VREF(+)GH
and VREF(–)GH to be referenced to Device GND. As DAC G
and DAC H input codes vary from 000␣ .␣ .␣ .␣ 000 to 111␣ .␣ .␣ .␣ 111,
VOUTG and VOUTH vary from –10 V to +10 V with respect to
Device GND. Device GND is also connected to DUTGND.
When the AD7841 is cleared, VOUTG and VOUTH are cleared to
0 V with respect to Device GND.
Programmable Reference Generation for the AD7841 in an
ATE Application
The AD7841 is particularly suited for use in an automated test
environment. The reference input for the AD7841 octal 14-bit
DAC requires three differential references for the eight DACs.
Programmable references may be a requirement in some ATE
applications as the offset and gain errors at the output of a DAC
can be adjusted by varying the voltages on the reference pins of
the DAC. To trim offset errors, the DAC is loaded with the
digital code 000␣ .␣ .␣ .␣ 000 and the voltage on the VREF(–) pin is
adjusted until the desired negative output voltage is obtained.
To trim out gain errors, first the offset error is trimmed. Then
the DAC is loaded with the code 111␣ .␣ .␣ .␣ 111 and the voltage
on the VREF(+) pin is adjusted until the desired full-scale voltage
minus one LSB is obtained.
It is not uncommon in ATE design, to have other circuitry at
the output of the AD7841 that can have offset and gain errors of
up to say ± 300 mV. These offset and gain errors can be easily
removed by adjusting the reference voltages of the AD7841.
The AD7841 uses nominal reference values of ± 5 V to achieve
an output span of ± 10 V. Since the AD7841 has a gain of two
from the reference inputs to the DAC output, adjusting the
reference voltages by ± 150 mV will adjust the DAC offset and
gain by ± 300 mV.
There are a number of suitable 8- and 10-bit DACs available
that would be suitable to drive the reference inputs of the
AD7841, such as the AD7804, a quad 10-bit digital-to-analog
converter with serial load capabilities. The voltage output from
this DAC is in the form of VBIAS ± VSWING and rail-to-rail opera-
tion is achievable. The voltage reference for this DAC can be
internally generated or provided externally. This DAC also
contains an 8-bit SUB DAC which can be used to shift the
complete transfer function of each DAC around the VBIAS point.
This can be used as a fine trim on the output voltage. In this
application two AD7804s are required to provide programmable
reference capability for all eight DACs. One AD7804 is used to
drive the VREF(+) pins and the second package used to drive the
VREF(–) pins.
Another suitable DAC for providing programmable reference
capability is the AD8803. This is an octal 8-bit trimDAC® and
provides independent control of both the top and bottom ends
of the trimDAC. This is helpful in maximizing the resolution of
devices with a limited allowable voltage control range.
TrimDAC is a registered trademark of Analog Devices, Inc.
REV. 0
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7841.PDF ] | |
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