PDF AD7837 Data sheet ( Hoja de datos )

Número de pieza	AD7837
Descripción	LC2MOS Complete/ Dual 12-Bit MDACs
Fabricantes	Analog Devices
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No Preview Available ! a LC2MOS Complete, Dual 12-Bit MDACs AD7837/AD7847 FEATURES Two 12-Bit MDACs with Output Amplifiers 4-Quadrant Multiplication Space-Saving 0.3", 24-Lead DIP and 24-Terminal SOIC Package Parallel Loading Structure: AD7847 (8 + 4) Loading Structure: AD7837 APPLICATIONS Automatic Test Equipment Function Generation Waveform Reconstruction Programmable Power Supplies Synchro Applications GENERAL DESCRIPTION The AD7837/AD7847 is a complete, dual, 12-bit multiplying digital-to-analog converter with output amplifiers on a mono- lithic CMOS chip. No external user trims are required to achieve full specified performance. Both parts are microprocessor compatible, with high speed data latches and interface logic. The AD7847 accepts 12-bit parallel data which is loaded into the respective DAC latch using the WR input and a separate Chip Select input for each DAC. The AD7837 has a double-buffered 8-bit bus interface structure with data loaded to the respective input latch in two write opera- tions. An asynchronous LDAC signal on the AD7837 updates the DAC latches and analog outputs. The output amplifiers are capable of developing ± 10 V across a 2 kΩ load. They are internally compensated with low input off- set voltage due to laser trimming at wafer level. The amplifier feedback resistors are internally connected to VOUT on the AD7847. The AD7837/AD7847 is fabricated in Linear Compatible CMOS (LC2MOS), an advanced, mixed technology process that com- bines precision bipolar circuits with low power CMOS logic. A novel low leakage configuration (U.S. Patent No. 4,590,456) ensures low offset errors over the specified temperature range. FUNCTIONAL BLOCK DIAGRAMS VDD AD7837 VREFA VREFB DB0 DB7 LDAC CS WR A0 A1 CONTROL LOGIC DGND MS INPUT LATCH LS INPUT LATCH 48 DAC LATCH A 12 DAC A DAC B 12 DAC LATCH B 48 MS INPUT LATCH LS INPUT LATCH RFBA VOUTA AGNDA RFBB VOUTB AGNDB VSS VDD AD7847 VREFA VREFB DB0 DB11 WR CSA CSB CONTROL LOGIC DAC LATCH A DAC A DAC B DAC LATCH B VOUTA AGNDA VOUTB AGNDB DGND VSS PRODUCT HIGHLIGHTS 1. The AD7837/AD7847 is a dual, 12-bit, voltage-out MDAC on a single chip. This single chip design offers considerable space saving and increased reliability over multichip designs. 2. The AD7837 and the AD7847 provide a fast versatile inter- face to 8-bit or 16-bit data bus structures. REV. C Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 2000 1 page Pin 11 12 13 14 15 16 17 18 19 10 11 12 13 14–24 AD7837/AD7847 AD7847 PIN FUNCTION DESCRIPTION (DIP AND SOIC PIN NUMBERS) Mnemonic CSA CSB VREFA VOUTA AGNDA VDD VSS AGNDB VOUTB VREFB DGND DB11 WR DB10–DB0 Description Chip Select Input for DAC A. Active low logic input. DAC A is selected when this input is low. Chip Select Input for DAC B. Active low logic input. DAC B is selected when this input is low. Reference Input Voltage for DAC A. This may be an ac or dc signal. Analog Output Voltage from DAC A. Analog Ground for DAC A. Positive Power Supply. Negative Power Supply. Analog Ground for DAC B. Analog Output Voltage from DAC B. Reference Input Voltage for DAC B. This may be an ac or dc signal. Digital Ground. Data Bit 11 (MSB). Write Input. WR is a positive edge triggered input which is used in conjunction with CSA and CSB to write data to the DAC latches. Data Bit 10 to Data Bit 0 (LSB). AD7837 PIN CONFIGURATION DIP AND SOIC CS 1 24 DB0 RFBA 2 23 DB1 VREFA 3 22 DB2 VOUTA 4 21 DB3 AGNDA VDD VSS 5 AD7837 20 DB4 6 TOP VIEW 19 DB5 7 (Not to Scale) 18 DB6 AGNDB 8 17 DB7 VOUTB 9 16 A0 VREFB 10 DGND 11 15 A1 14 LDAC RFBB 12 13 WR AD7847 PIN CONFIGURATION DIP AND SOIC CSA 1 24 DB0 CSB 2 23 DB1 VREFA 3 VOUTA 4 22 DB2 21 DB3 AGNDA VDD VSS 5 AD7847 20 DB4 6 TOP VIEW 19 DB5 7 (Not to Scale) 18 DB6 AGNDB 8 17 DB7 VOUTB 9 VREFB 10 DGND 11 16 DB8 15 DB9 14 DB10 DB11 12 13 WR REV. C –5– 5 Page 8086 ALE WR ADDRESS BUS 16 BIT LATCH ADDRESS DECODE CSA CSB AD7847* WR DB11 DB0 AD15 AD0 ADDRESS/DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY Figure 20. AD7847 to 8086 Interface AD7847–MC68000 Interface Figure 21 shows an interface between the AD7847 and the MC68000. Once again a single MOVE instruction loads the 12-bit word into the selected DAC latch. CSA and CSB are AND-gated to provide a DTACK signal when either DAC latch is selected. A23 ADDRESS BUS A1 MC68000 AS DTACK LDS R/W ADDRESS DECODE EN CSA CSB AD7847 WR DB11 DB0 D15 DATA BUS D0 ADDITIONAL PINS OMITTED FOR CLARITY Figure 21. AD7847 to MC68000 Interface AD7847–TMS320C10 Interface Figure 22 shows an interface between the AD7847 and the TMS320C10 DSP processor. A single OUT instruction loads the 12-bit word into the selected DAC latch. A11 A0 TMS320C10 MEN WE ADDRESS BUS ADDRESS DECODE EN CSA CSB AD7847 WR DB11 DB0 D15 DATA BUS D0 ADDITIONAL PINS OMITTED FOR CLARITY Figure 22. AD7847 to TMS320C10 Interface AD7837/AD7847 MICROPROCESSOR INTERFACING–AD7837 Figures 23 to 25 show the AD7837 configured for interfacing to microprocessors with 8-bit data bus systems. In all cases, data is right-justified and the AD7837 is memory-mapped with the two lowest address lines of the microprocessor address bus driving the A0 and A1 inputs of the AD7837. Five separate memory addresses are required, one for the each MS latch and one for each LS latch and one for the common LDAC input. Data is written to the respective input latch in two write operations. Either high byte or low byte data can be written first to the input latch. A write to the AD7837 LDAC address transfers the data from the input latches to the respective DAC latches and updates both analog outputs. Alternatively, the LDAC input can be asynchronous and can be common to several AD7837s for simultaneous updating of a number of voltage channels. AD7837–8051/8088 Interface Figure 23 shows the connection diagram for interfacing the AD7837 to both the 8051 and the 8088. On the 8051, the signal PSEN is used to enable the address decoder while DEN is used on the 8088. A15 ADDRESS BUS A8 8051/8088 PSEN OR DEN ADDRESS DECODE EN A0 A1 CS LDAC ALE WR OCTAL LATCH AD7837 WR DB7 DB0 AD7 AD0 ADDRESS/DATA BUS ADDITIONAL PINS OMITTED FOR CLARITY Figure 23. AD7837 to 8051/8088 Interface AD7837–MC68008 Interface An interface between the AD7837 and the MC68008 is shown in Figure 24. In the diagram shown, the LDAC signal is derived from an asynchronous timer but this can be derived from the address decoder as in the previous interface diagram. TIMER A19 ADDRESS BUS A0 MC68008 AS ADDRESS DECODE EN A0 A1 CS LDAC DTACK DS R/W AD7837 WR DB7 DB0 D7 DATA BUS D0 *ADDITIONAL PINS OMITTED FOR CLARITY Figure 24. AD7837 to 68008 Interface REV. C –11– 11 Page

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