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PDF AD7822 Data sheet ( Hoja de datos )
| Número de pieza | AD7822 | |
| Descripción | 3 V/5 V/ 2 MSPS/ 8-Bit/ 1-/ 4-/ 8-Channel Sampling ADCs | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7822 (archivo pdf) en la parte inferior de esta página. Total 18 Páginas | ||
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a 3 V/5 V, 2 MSPS, 8-Bit, 1-, 4-, 8-Channel
Sampling ADCs
AD7822/AD7825/AD7829
FEATURES
8-Bit Half-Flash ADC with 420 ns Conversion Time
1, 4 and 8 Single-Ended Analog Input Channels
Available with Input Offset Adjust
On-Chip Track-and-Hold
SNR Performance Given for Input Frequencies Up to
10 MHz
On-Chip Reference (2.5 V)
Automatic Power-Down at the End of Conversion
Wide Operating Supply Range
3 V ؎ 10% and 5 V ؎ 10%
Input Ranges
0 V to 2 V p-p, VDD = 3 V ؎ 10%
0 V to 2.5 V p-p, VDD = 5 V ؎ 10%
Flexible Parallel Interface with EOC Pulse to Allow
Stand-Alone Operation
APPLICATIONS
Data Acquisition Systems, DSP Front Ends
Disk Drives
Mobile Communication Systems, Subsampling
Applications
FUNCTIONAL BLOCK DIAGRAM
CONVST EOC A0* A1* A2* PD*
VDD
CONTROL
LOGIC
COMP
2.5V
REF
VIN1
VIN2*
VIN3*
VIN4*
VIN5*
VIN6*
VIN7*
VIN8*
INPUT
MUX
T/H
8-BIT
HALF
FLASH
ADC
BUF
PARALLEL
PORT
VMID AGND DGND
*A0, A1
*A2
*PD
*VIN2 TO VIN4
*VIN4 TO VIN8
AD7825/AD7829
AD7829
AD7822/AD7825
AD7825/AD7829
AD7829
CS RD
VREFIN/REFOUT
DB7
DB0
GENERAL DESCRIPTION
The AD7822, AD7825, and AD7829 are high speed, 1-, 4-, and
8-channel, microprocessor-compatible, 8-bit analog-to-digital
converters with a maximum throughput of 2 MSPS. The AD7822,
AD7825, and AD7829 contain an on-chip reference of 2.5 V
(2% tolerance), a track/hold amplifier, a 420 ns 8-bit half-flash
ADC and a high speed parallel interface. The converters can
operate from a single 3 V ± 10% and 5 V ± 10% supply.
The AD7822, AD7825, and AD7829 combine the convert start
and power-down functions at one pin, i.e., the CONVST pin.
This allows a unique automatic power-down at the end of a
conversion to be implemented. The logic level on the CONVST
pin is sampled after the end of a conversion when an EOC (End
of Conversion) signal goes high, and if it is logic low at that
point, the ADC is powered down. The AD7822 and AD7825
also have a separate power-down pin. (See Operating Modes
section of the data sheet.)
The parallel interface is designed to allow easy interfacing to
microprocessors and DSPs. Using only address decoding logic,
the parts are easily mapped into the microprocessor address
space. The EOC pulse allows the ADCs to be used in a stand-
alone manner. (See Parallel Interface section of the data sheet.)
The AD7822 and AD7825 are available in a 20-/24-lead 0.3"
wide, plastic dual-in-line package (DIP), a 20-/24-lead small
outline IC (SOIC) and a 20-/24-lead thin shrink small outline
package (TSSOP). The AD7829 is available in a 28-lead 0.6"
wide, plastic dual-in-line package (DIP), a 28-lead small outline
IC (SOIC) and in a 28-lead thin shrink small outline package
(TSSOP).
PRODUCT HIGHLIGHTS
1. Fast Conversion Time
The AD7822, AD7825, and AD7829 have a conversion time
of 420 ns. Faster conversion times maximize the DSP pro-
cessing time in a real time system.
2. Analog Input Span Adjustment
The VMID pin allows the user to offset the input span. This
feature can reduce the requirements of single supply op amps
and take into account any system offsets.
3. FPBW (Full Power Bandwidth) of Track and Hold
The track-and-hold amplifier has an excellent high frequency
performance. The AD7822, AD7825, and AD7829 are
capable of converting full-scale input signals up to a fre-
quency of 10 MHz. This makes the parts ideally suited to
subsampling applications.
4. Channel Selection
Channel selection is made without the necessity of writing to
the part.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
Mnemonic
VIN1 to VIN8
VDD
AGND
DGND
CONVST
EOC
CS
PD
RD
A0–A2
DB0–DB7
VREF IN/OUT
AD7822/AD7825/AD7829
PIN FUNCTION DESCRIPTIONS
Description
Analog Input Channels. The AD7822 has a single input channel; the AD7825 and AD7829 have four and eight
analog input channels respectively. The inputs have an input span of 2.5 V and 2 V depending on the sup-
ply voltage (VDD). This span may be centered anywhere in the range AGND to VDD using the VMID Pin. The
default input range (VMID unconnected) is AGND to 2 V (VDD = 3 V ± 10%) or AGND to 2.5 V (VDD = 5 V
± 10%). See Analog Input section of the data sheet for more information.
Positive supply voltage, 3 V ± 10% and 5 V ± 10%.
Analog Ground. Ground reference for track/hold, comparators, reference circuit and multiplexer.
Digital Ground. Ground reference for digital circuitry.
Logic Input Signal. The convert start signal initiates an 8-bit analog-to-digital conversion on the falling edge of
this signal. The falling edge of this signal places the track/hold in hold mode. The track/hold goes into track
mode again 120 ns after the start of a conversion. The state of the CONVST signal is checked at the end of
a conversion. If it is logic low, the AD7822/AD7825/AD7829 will power down. (See Operating Mode section of
the data sheet.)
Logic Output. The End of Conversion signal indicates when a conversion has finished. The signal can be used
to interrupt a microcontroller when a conversion has finished or latch data into a gate array. (See Parallel Inter-
face section of this data sheet.)
Logic input signal. The chip select signal is used to enable the parallel port of the AD7822, AD7825, and AD7829.
This is necessary if the ADC is sharing a common data bus with another device.
Logic Input. The Power-Down pin is present on the AD7822 and AD7825 only. Bringing the PD pin low
places the AD7822 and AD7825 in Power-Down mode. The ADCs will power-up when PD is brought logic
high again.
Logic Input Signal. The read signal is used to take the output buffers out of their high impedance state and
drive data onto the data bus. The signal is internally gated with the CS signal. Both RD and CS must be logic
low to enable the data bus.
Channel Address Inputs. The address of the next multiplexer channel must be present on these inputs when the
RD signal goes low.
Data Output Lines. They are normally held in a high impedance state. Data is driven onto the data bus when
both RD and CS go active low.
Analog Input and Output. An external reference can be connected to the AD7822, AD7825, and AD7829 at this
pin. The on-chip reference is also available at this pin.
DB2 1
20 DB3
DB1 2
19 DB4
DB0 3
18 DB5
CONVST 4
17 DB6
CS 5 AD7822 16 DB7
RD
6
TOP VIEW
(Not to Scale)
15
AGND
DGND 7
14 VDD
EOC 8
13 VREF
PD 9
12 VMID
NC 10
11 VIN1
NC = NO CONNECT
PIN CONFIGURATIONS
DIP/SOIC/TSSOP
DB2 1
24 DB3
DB1 2
23 DB4
DB0 3
22 DB5
CONVST 4
21 DB6
CS 5 AD7825 20 DB7
RD 6 TOP VIEW 19 AGND
DGND 7 (Not to Scale) 18 VDD
EOC 8
17 VREF
A1 9
16 VMID
A0 10
PD 11
15 VIN1
14 VIN2
VIN4 12
13 VIN3
DB2 1
28 DB3
DB1 2
27 DB4
DB0 3
26 DB5
CONVST 4
25 DB6
CS 5
24 DB7
RD 6
23 AGND
DGND 7 AD7829 22 VDD
EOC
TOP VIEW
8 (Not to Scale) 21 VREF
A2 9
20 VMID
A1 10
19 VIN1
A0 11
18 VIN2
VIN8 12
17 VIN3
VIN7 13
16 VIN4
VIN6 14
15 VIN5
REV. A
–5–
5 Page 
AD7822/AD7825/AD7829
Figure 16 shows how to power up the AD7822 or AD7825 when
VDD is first connected or after the ADCs have been powered
down using the PD pin, or the CONVST pin, with either the
on-chip or an external reference. When the supplies are first
connected or after the part has been powered down by the PD
pin, only a rising edge on the PD pin will cause the part to
power up. When the part has been powered down using the
CONVST pin, a rising edge on either the PD pin or the CONVST
pin will power the part up again.
As with the AD7829, when using an external reference with the
AD7822 or AD7825, the falling edge of CONVST may occur
before the required power-up time has elapsed, however, if this
is the case, the conversion will not be initiated on the falling edge
of CONVST, but rather at the moment when the part has powered
up completely, i.e., after 1 µs. If the falling edge of CONVST
occurs after the required power-up time has elapsed, it is upon
this falling edge that a conversion is initiated. When using the
on-chip reference it is necessary to wait the required power-
up time of approximately 25 µs before initiating a conversion;
i.e., a falling edge on CONVST may not occur before the
required power-up time has elapsed, when supplies are first
connected to the AD7822 or AD7825, or when the ADCs have
been powered down using the PD pin or the CONVST pin as
shown in Figure 16.
VDD
PD
CONVST
EXTERNAL REFERENCE
tPOWER-UP
1s
tPOWER-UP
1s
CONVST
tPOWER-UP tCONVERT
1s
330ns
POWER-DOWN
tCYCLE
10s @ 100kSPS
Figure 17. Automatic Power-Down
For example, if the AD7822 is operated in a continuous sam-
pling mode, with a throughput rate of 100 kSPS and using an
external reference, the power consumption is calculated as fol-
lows. The power dissipation during normal operation is 36 mW,
VDD = 3 V. If the power-up time is 1 µs and the conversion time
is 330 ns (@ +25°C), the AD7822 can be said to dissipate
36 mW for 1.33 µs (worst case) during each conversion cycle.
If the throughput rate is 100 kSPS, the cycle time is 10 µs
and the average power dissipated during each cycle is (1.33/10)
× (36 mW) = 4.79 mW.
Figure 18 shows the power vs. throughput rate for automatic
full power-down.
100
10
1
0.1
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
VDD
PD
CONVST
ON-CHIP REFERENCE
tPOWER-UP
25s
tPOWER-UP
25s
CONVERSION
INITIATED HERE
CONVERSION
INITIATED HERE
Figure 16. AD7822/AD7825 Power-Up Time
POWER VS. THROUGHPUT
Superior power performance can be achieved by using the auto-
matic power-down (Mode 2) at the end of a conversion—see
Operating Modes section of the data sheet.
Figure 17 shows how the automatic power-down is implemented
using the CONVST signal to achieve the optimum power per-
formance for the AD7822, AD7825, and AD7829. The duration
of the CONVST pulse is set to be equal to or less than the
power-up time of the devices—see Operating Modes section. As
the throughput rate is reduced, the device remains in its power-
down state longer and the average power consumption over time
drops accordingly.
0
0 50 100 150 200 250 300 350 400 450 500
THROUGHPUT – kSPS
Figure 18. AD7822/AD7825/AD7829 Power vs. Throughput
0
2048 POINT FFT
–10
SAMPLING
2MSPS
FIN = 200kHz
–20
–30
–40
–50
–60
–70
–80
FREQUENCY – kHz
Figure 19. AD7822/AD7825/AD7829 SNR
REV. A
–11–
11 Page | ||
| Páginas | Total 18 Páginas | |
| PDF Descargar | [ Datasheet AD7822.PDF ] | |
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