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PDF AD7755 Data sheet ( Hoja de datos )
| Número de pieza | AD7755 | |
| Descripción | Energy Metering IC with Pulse Output | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
Energy Metering IC
with Pulse Output
AD7755*
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of
500 to 1
The AD7755 Supplies Average Real Power on the
Frequency Outputs F1 and F2
The High Frequency Output CF Is Intended for
Calibration and Supplies Instantaneous Real Power
The Logic Output REVP Can Be Used to Indicate a
Potential Miswiring or Negative Power
Direct Drive for Electromechanical Counters and
Two Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of Shunt and Burden Resistance
Proprietary ADCs and DSP Provide High Accuracy over
Large Variations in Environmental Conditions and
Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V 6 8% (30 ppm/8C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low Cost CMOS Process
GENERAL DESCRIPTION
The AD7755 is a high accuracy electrical energy measurement
IC. The part specifications surpass the accuracy requirements
as quoted in the IEC1036 standard. See Analog Devices’
Application Note AN-559 for a description of an IEC1036
watt-hour meter reference design.
The only analog circuitry used in the AD7755 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The AD7755 supplies average real power information on the
low frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes, or interfacing to an MCU.
The AD7755 includes a power supply monitoring circuit on the
AVDD supply pin. The AD7755 will remain in a reset condition
until the supply voltage on AVDD reaches 4 V. If the supply falls
below 4 V, the AD7755 will also be reset and no pulses will be
issued on F1, F2 and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are phase matched whether the HPF in Chan-
nel 1 is on or off. An internal no-load threshold ensures that the
AD7755 does not exhibit any creep when there is no load.
The AD7755 is available in 24-lead DIP and SSOP packages.
G0 G1
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND
AC/DC
DVDD DGND
V1P
V1N
V2P
V2N
AD7755
POWER
SUPPLY MONITOR
PHASE
CORRECTION
. . .110101. . .
ADC
⌽
PGA
x1, x2, x8, x16
HPF
MULTIPLIER
. . .11011001. . .
ADC
SIGNAL
PROCESSING
BLOCK
LPF
2.5V
4k⍀
REFERENCE
DIGITAL-TO-FREQUENCY
CONVERTER
RESET
REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2
*U.S. Patents 5,745,323, 5,760,617, 5,862,069, 5,872,469.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Pin No.
1
Mnemonic
DVDD
2 AC/DC
3 AVDD
4, 19
5, 6
NC
V1P, V1N
7, 8 V2N, V2P
9 RESET
10 REFIN/OUT
11 AGND
12
13, 14
SCF
S1, S0
15, 16
17
G1, G0
CLKIN
18 CLKOUT
20 REVP
AD7755
PIN FUNCTION DESCRIPTIONS
Description
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7755.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
High Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current channel).
A logic one on this pin enables the HPF. The associated phase response of this filter has been inter-
nally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be enabled in
power metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7755.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made to
minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin should
be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
No Connect.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs with
a maximum differential signal level of ± 470 mV for specified operation. Channel 1 also has a PGA and
the gain selections are outlined in Table I. The maximum signal level at these pins is ± 1 V with respect
to AGND. Both inputs have internal ESD protection circuitry and in addition an overvoltage of ± 6 V
can be sustained on these inputs without risk of permanent damage.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differential
input pair. The maximum differential input voltage is ± 660 mV for specified operation. The maximum
signal level at these pins is ± 1 V with respect to AGND. Both inputs have internal ESD protection
circuitry and an overvoltage of ± 6 V can also be sustained on these inputs without risk of permanent
damage.
Reset Pin for the AD7755. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7755 internal registers.
This pin provides access to the on-chip voltage reference. The on-chip reference has a nominal value
of 2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may
also be connected at this pin. In either case this pin should be decoupled to AGND with a 1 µF
ceramic capacitor and 100 nF ceramic capacitor.
This provides the ground reference for the analog circuitry in the AD7755, i.e., ADCs and reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the ground
reference for all analog circuitry, e.g., antialiasing filters, current and voltage transducers, etc. For
good noise suppression the analog ground plane should only connected to the digital ground plane at
one point. A star ground configuration will help to keep noisy digital currents away from the analog
circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration output
CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency con-
version. This offers the designer greater flexibility when designing the energy meter. See Selecting a
Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for Channel 1, i.e., V1. The possible
gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7755. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitance of between 22 pF and
33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7755. The CLKOUT pin can drive one CMOS load when an external clock is supplied at
CLKIN or by the gate oscillator circuit.
This logic output will go logic high when negative power is detected, i.e., when the phase angle between
the voltage and current signals is greater that 90°. This output is not latched and will be reset when
positive power is once again detected. The output will go high or low at the same time as a pulse is
issued on CF.
REV. B
–5–
5 Page 
AD7755
Using Equations 1 and 2, the real power P can be expressed in
terms of its fundamental real power (P1) and harmonic real
power (PH).
P = P1 + PH
where:
P1 = V1 × I1 cos φ1
φ1 = α1 – β1
(3)
and ∝
PH = ∑Vh × Ih cos φh
h ≠1
φh = αh – βh
(4)
As can be seen from Equation 4 above, a harmonic real power
component is generated for every harmonic, provided that har-
monic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid, therefore the harmonic
real power must also correctly account for power factor since it
is made up of a series of pure sinusoids.
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
Table I. Gain Selection for Channel 1
Maximum
G1 G0 Gain Differential Signal
001
012
108
1 1 16
± 470 mV
± 235 mV
± 60 mV
± 30 mV
Channel V2 (Voltage Channel )
The output of the line voltage transducer is connected to the
AD7755 at this analog input. Channel V2 is a fully differential
voltage input. The maximum peak differential signal on Chan-
nel 2 is ± 660 mV. Figure 23 illustrates the maximum signal
levels that can be connected to the AD7755 Channel 2.
V2
+660mV
VCM
–660mV
DIFFERENTIAL INPUT
؎660mV MAX PEAK
V2P
V2 V2N
COMMON-MODE
؎100mV MAX
VCM
AGND
ANALOG INPUTS
Channel V1 (Current Channel )
The voltage output from the current transducer is connected to
the AD7755 here. Channel V1 is a fully differential voltage
input. V1P is the positive input with respect to V1N.
The maximum peak differential signal on Channel 1 should be
less than ± 470 mV (330 mV rms for a pure sinusoidal signal) for
specified operation. Note that Channel 1 has a programmable
gain amplifier (PGA) with user selectable gain of 1, 2, 8 or 16
(see Table I). These gains facilitate easy transducer interfacing.
V1
+470mV
VCM
–470mV
DIFFERENTIAL INPUT
؎470mV MAX PEAK
COMMON-MODE
؎100mV MAX
V1P
V1 V1N
VCM
AGND
Figure 22. Maximum Signal Levels, Channel 1, Gain = 1
The diagram in Figure 22 illustrates the maximum signal levels
on V1P and V1N. The maximum differential voltage is ±470 mV
divided by the gain selection. The differential voltage signal on
the inputs must be referenced to a common mode, e.g. AGND.
The maximum common mode signal is ± 100 mV as shown in
Figure 22.
Figure 23. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
AD7755 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However best results are
achieved using a common mode equal to AGND.
Typical Connection Diagrams
Figure 24 shows a typical connection diagram for Channel V1.
A CT (current transformer) is the current transducer selected for
this example. Notice the common-mode voltage for Channel 1
is AGND and is derived by center tapping the burden resistor
to AGND. This provides the complementary analog input sig-
nals for V1P and V1N. The CT turns ratio and burden resistor
Rb are selected to give a peak differential voltage of ± 470 mV/
Gain at maximum load.
CT
Rb
Rf
؎470mV
GAIN
V1P
Cf
V1N
IP AGND
PHASE NEUTRAL
Rf Cf
Figure 24. Typical Connection for Channel 1
REV. B
–11–
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| PDF Descargar | [ Datasheet AD7755.PDF ] | |
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