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PDF AD7751 Data sheet ( Hoja de datos )
| Número de pieza | AD7751 | |
| Descripción | Energy Metering IC With On-Chip Fault Detection | |
| Fabricantes | Analog Devices | |
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a
Energy Metering IC
With On-Chip Fault Detection
AD7751*
FEATURES
High Accuracy, Supports 50 Hz/60 Hz IEC 687/1036
Less than 0.1% Error Over a Dynamic Range of 500 to 1
Supplies Average Real Power on the Frequency
Outputs F1 and F2
High-Frequency Output CF Is Intended for Calibration
and Supplies Instantaneous Real Power
Continuous Monitoring of the Phase and Neutral
Current Allows Fault Detection in Two-Wire
Distribution Systems
AD7751 Uses the Larger of the Two Currents (Phase
or Neutral) to Bill—Even During a Fault Condition
Two Logic Outputs (FAULT and REVP) Can be Used to
Indicate a Potential Miswiring or Fault Condition
Direct Drive for Electromechanical Counters and
Two-Phase Stepper Motors (F1 and F2)
A PGA in the Current Channel Allows the Use of Small
Values of Shunt and Burden Resistance
Proprietary ADCs and DSP Provide High Accuracy Over
Large Variations in Environmental Conditions and Time
On-Chip Power Supply Monitoring
On-Chip Creep Protection (No Load Threshold)
On-Chip Reference 2.5 V ؎ 8% (30 ppm/؇C Typical)
with External Overdrive Capability
Single 5 V Supply, Low Power (15 mW Typical)
Low-Cost CMOS Process
GENERAL DESCRIPTION
The AD7751 is a high-accuracy fault-tolerant electrical energy
measurement IC that is intended for use with 2-wire distribution
systems. The part specifications surpass the accuracy require-
ments as quoted in the IEC1036 standard.
The only analog circuitry used in the AD7751 is in the ADCs
and reference circuit. All other signal processing (e.g., multipli-
cation and filtering) is carried out in the digital domain. This
approach provides superior stability and accuracy over extremes
in environmental conditions and over time.
The AD7751 incorporates a novel fault detection scheme that
warns of fault conditions and allows the AD7751 to continue
accurate billing during a fault event. The AD7751 does this
by continuously monitoring both the phase and neutral (re-
turn) currents. A fault is indicated when these currents differ by
more than 12.5%. Billing is continued using the larger of the
two currents.
The AD7751 supplies average real power information on the
low-frequency outputs F1 and F2. These logic outputs may be
used to directly drive an electromechanical counter or interface
to an MCU. The CF logic output gives instantaneous real power
information. This output is intended to be used for calibration
purposes.
The AD7751 includes a power supply monitoring circuit on the
AVDD supply pin. The AD7751 will remain in a reset condition
until the supply voltage on AVDD reaches 4 V. If the supply falls
below 4 V, the AD7751 will also be reset and no pulses will be
issued on F1, F2, and CF.
Internal phase matching circuitry ensures that the voltage and
current channels are matched whether the HPF in Channel 1 is
on or off. The AD7751 also has anticreep protection.
The AD7751 is available in 24-lead DIP and SSOP packages.
FUNCTIONAL BLOCK DIAGRAM
G0 G1
AVDD AGND
FAULT
AC/DC DVDD DGND
AD7751
POWER
SUPPLY MONITOR
SIGNAL
V1A
A< >B
...110101... A
PROCESSING
BLOCK
ADC
HPF
PGA
A >B
V1N ؋1, ؋2, ؋8, ؋16
⌽
V1B
PGA
ADC
...110101... B
B>A
PHASE
CORRECTION
MULTIPLIER
؋1, ؋2, ؋8, ؋16
LPF
V2P ...11011001...
ADC
V2N DIGITAL-TO-FREQUENCY
2.5V
4k⍀
CONVERTER
REFERENCE
REFIN/OUT CLKIN CLKOUT SCF S0 S1 REVP CF F1 F2 RESET
*US Patent 5,745,323; 5,760,617; 5,862,069; 5,872,469.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2000
1 page  
Pin No.
1
Mnemonic
DVDD
2 AC/DC
3 AVDD
4, 5 V1A, V1B
6 V1N
7, 8 V2N, V2P
9 RESET
10 REFIN/OUT
11 AGND
12
13, 14
SCF
S1, S0
15, 16
17
G1, G0
CLKIN
18 CLKOUT
19 FAULT
REV. A
AD7751
PIN FUNCTION DESCRIPTIONS
Description
Digital Power Supply. This pin provides the supply voltage for the digital circuitry in the AD7751.
The supply voltage should be maintained at 5 V ± 5% for specified operation. This pin should be
decoupled with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
High-Pass Filter Select. This logic input is used to enable the HPF in Channel 1 (the current
channel). A Logic 1 on this pin enables the HPF. The associated phase response of this filter has
been internally compensated over a frequency range of 45 Hz to 1 kHz. The HPF filter should be
enabled in energy metering applications.
Analog Power Supply. This pin provides the supply voltage for the analog circuitry in the AD7751.
The supply should be maintained at 5 V ± 5% for specified operation. Every effort should be made
to minimize power supply ripple and noise at this pin by the use of proper decoupling. This pin
should be decoupled to AGND with a 10 µF capacitor in parallel with a ceramic 100 nF capacitor.
Analog Inputs for Channel 1 (Current Channel). These inputs are fully differential voltage inputs
with a maximum signal level of ± 660 mV with respect to Pin V1N for specified operation. The
maximum signal level at these pins is ± 1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of ± 6 V can also be sustained on these inputs without risk of
permanent damage.
Negative Input Pin for Differential Voltage Inputs V1A and V1B. The maximum signal level at this
pin is ± 1 V with respect to AGND. The input has internal ESD protection circuitry and in addition,
an overvoltage of ± 6 V can be sustained without risk of permanent damage. This input should be
directly connected to the burden resistor and held at a fixed potential, i.e., AGND. See Analog
Input section.
Negative and Positive Inputs for Channel 2 (Voltage Channel). These inputs provide a fully differ-
ential input pair. The maximum differential input voltage is ± 660 mV for specified operation. The
maximum signal level at these pins is ± 1 V with respect to AGND. Both inputs have internal ESD
protection circuitry and an overvoltage of ± 6 V can also be sustained on these inputs without risk of
permanent damage.
Reset Pin for the AD7751. A logic low on this pin will hold the ADCs and digital circuitry in a reset
condition. Bringing this pin logic low will clear the AD7751 internal registers.
Provides Access to the On-Chip Voltage Reference. The on-chip reference has a nominal value of
2.5 V ± 8% and a typical temperature coefficient of 30 ppm/°C. An external reference source may also
be connected at this pin. In either case, this pin should be decoupled to AGND with a 1 µF ceramic
capacitor and 100 nF ceramic capacitor.
Provides the Ground Reference for the Analog Circuitry in the AD7751, i.e., ADCs and Reference.
This pin should be tied to the analog ground plane of the PCB. The analog ground plane is the
ground reference for all analog circuitry, e.g., antialiasing filters, current and voltage transduc-
ers, etc. For good noise suppression the analog ground plane should only be connected to the digital
ground plane at one point. A star ground configuration will help to keep noisy digital return currents
away from the analog circuits.
Select Calibration Frequency. This logic input is used to select the frequency on the calibration
output CF. Table IV shows how the calibration frequencies are selected.
These logic inputs are used to select one of four possible frequencies for the digital-to-frequency
conversion. This offers the designer greater flexibility when designing the energy meter. See Select-
ing a Frequency for an Energy Meter Application section.
These logic inputs are used to select one of four possible gains for the analog inputs V1A and V1B.
The possible gains are 1, 2, 8 and 16. See Analog Input section.
An external clock can be provided at this logic input. Alternatively, a parallel resonant AT crystal can
be connected across CLKIN and CLKOUT to provide a clock source for the AD7751. The clock
frequency for specified operation is 3.579545 MHz. Crystal load capacitors of between 22 pF
and 33 pF (ceramic) should be used with the gate oscillator circuit.
A crystal can be connected across this pin and CLKIN as described above to provide a clock source
for the AD7751. The CLKOUT pin can drive one CMOS load when an external clock is supplied
at CLKIN or by gate oscillator circuit.
This logic output will go active high when a fault condition occurs. A fault is defined as a condition
under which the signals on V1A and V1B differ by more than 12.5%. The logic output will be reset
to zero when a fault condition is no longer detected. See Fault Detection section.
–5–
5 Page 
AD7751
Using Equations 2 and 3, the real-power P can be expressed in
terms of its fundamental real power (P1) and harmonic real
power (PH).
P = P1 + PH
where:
P1 = V1 × I1 cos(φ1)
φ1 = α1 – β1
(4)
and
∞
PH = ∑ Vh × Ih × cos(φh )
h≠1
(5)
φh = αh – βh
As can be seen from Equation 5 above, a harmonic real-power
component is generated for every harmonic, provided that har-
monic is present in both the voltage and current waveforms.
The power factor calculation has previously been shown to be
accurate in the case of a pure sinusoid, therefore the harmonic
real power must also correctly account for power factor since it
is made up of a series of pure sinusoids.
Note that the input bandwidth of the analog inputs is 14 kHz
with a master clock frequency of 3.5795 MHz.
ANALOG INPUTS
Channel V2 (Voltage Channel)
The output of the line voltage transducer is connected to the
AD7751 at this analog input. Channel V2 is a fully differential
voltage input. The maximum peak differential signal on Chan-
nel 2 is ± 660 mV. Figure 4 illustrates the maximum signal levels
that can be connected to the AD7751 Channel 2.
V2
+600mV
VCM
–600mV
DIFFERENTIAL INPUT
؎600mV MAX PEAK
V2P
V2 V2N
COMMON-MODE
؎100mV MAX
VCM
AGND
Figure 4. Maximum Signal Levels, Channel 2
Channel 2 must be driven from a common-mode voltage, i.e.,
the differential voltage signal on the input must be referenced to
a common mode (usually AGND). The analog inputs of the
AD7751 can be driven with common-mode voltages of up to
100 mV with respect to AGND. However, best results are
achieved using a common mode equal to AGND.
Channel V1 (Current Channel)
The voltage outputs from the current transducers are connected
to the AD7751 here. Channel V1 has two voltage inputs, namely
V1A and V1B. These inputs are fully differential with respect to
V1N. However, at any one time only one is selected to perform
the power calculation—see Fault Detection section.
The analog inputs V1A, V1B, and V1N have the same maximum
signal level restrictions as V2P and V2N. However, Channel 1
has a programmable gain amplifier (PGA) with user-selectable
gains of 1, 2, 8, or 16—see Table I. These gains facilitate easy
transducer interfacing.
Figure 5 illustrates the maximum signal levels on V1A, V1B,
and V1N. The maximum differential voltage is ±660 mV divided
by the gain selection. Again, the differential voltage signal on the
inputs must be referenced to a common mode, e.g., AGND. The
maximum common-mode signal is ±100 mV as shown in Figure 5.
V1A, V1B
+660mV
GAIN
VCM
–660mV
GAIN
DIFFERENTIAL INPUT A
؎660mV/GAIN MAX PEAK
COMMON-MODE
؎100mV MAX
VCM
AGND
DIFFERENTIAL INPUT B
؎660mV/GAIN MAX PEAK
V1A
V1
V1N
V1
V1B
Figure 5. Maximum Signal Levels, Channel 1
Table I.
G1 G0
00
01
10
11
Gain
1
2
8
16
Maximum
Differential Signal
± 660 mV
± 330 mV
± 82 mV
± 41 mV
Typical Connection Diagrams
Figure 6 shows a typical connection diagram for Channel V1.
Here the analog inputs are being used to monitor both the
phase and neutral currents. Because of the large potential
difference between the phase and neutral, two CTs (current
transformers) must be used to provide the isolation. Notice
both CTs are referenced to AGND (analog ground), hence
the common-mode voltage is 0 V. The CT turns ratio and
burden resistor (Rb) are selected to give a peak differential
voltage of ± 660 mV/Gain.
CT Rf
IP IN AGND
Rb ؎660mV
GAIN
؎660mV
Rb GAIN
V1A
Cf
V1N
Cf
PHASE NEUTRAL
CT
Rf V1B
Figure 6. Typical Connection for Channel 1
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7751.PDF ] | |
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