PDF AD7729 Data sheet ( Hoja de datos )

Número de pieza	AD7729
Descripción	Dual Sigma-Delta ADC with Auxiliary DAC
Fabricantes	Analog Devices
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No Preview Available ! a Dual Sigma-Delta ADC with Auxiliary DAC AD7729 FEATURES +3 V Supply Voltage Baseband Serial Port (BSPORT) Differential IRx and QRx ADC Channels Two 15-Bit Sigma-Delta A/D Converters FIR Digital Filters 64 dB SNR Output Word Rate 270.83 kHz Twos Complement Coding On-Chip Offset Calibration Power-Down Mode Auxiliary D/A Converter Auxiliary Serial Port (ASPORT) On-Chip Voltage Reference Low Power 28-Lead TSSOP/28-Lead SOIC APPLICATIONS GSM Basestations Pagers GENERAL DESCRIPTION This monolithic 3 V CMOS device is a low power, two-channel, input port with signal conditioning. The receive path is com- posed of two high performance sigma-delta ADCs with digital filtering. A common bandgap reference feeds the ADCs. A control DAC is included for such functions as AFC. The auxil- iary functions can be accessed via the auxiliary port (ASPORT). This device is available in a 28-lead TSSOP package or a 28-lead SOIC package. FUNCTIONAL BLOCK DIAGRAM DVDD2 DVDD1 DGND AGND AVDD1 AVDD2 ASDI ASDIFS ASCLK ASDO ASDOFS ASE BSDI BSDIFS BSCLK BSDO BSDOFS BSE MCLK RxON RESETB AUXILIARY SERIAL INTERFACE 10-BIT AUXDAC BASEBAND SERIAL INTERFACE OFFSET ADJUST OFFSET ADJUST DECIMATION FIR DIGITAL FILTER DECIMATION FIR DIGITAL FILTER ⌺⌬ MODULATOR ⌺⌬ MODULATOR DIVIDE BY 2 MUX REFERENCE AUXDAC IRxP IRxN QRxP QRxN REFCAP REFOUT REV. 0 Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 781/329-4700 World Wide Web Site: http://www.analog.com Fax: 781/326-8703 © Analog Devices, Inc., 1998 1 page TIMING DIAGRAMS t1 t3 t2 Figure 2. Clock Timing 100␮A IOL TO OUTPUT PIN CL 15pF 100␮A IOH +2.1V Figure 3. Load Circuit for Timing Specifications AD7729 MCLK t1 t3 t2 ASCLK t5 t6 t4 ASCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). Figure 4. ASCLK MCLK t1 t3 t2 BSCLK t8 t9 t7 BSCLK IS INDIVIDUALLY PROGRAMMABLE IN FREQUENCY (MCLK/4 SHOWN HERE). Figure 5. BSCLK ASE (I) ASCLK (O) THREE-STATE t 10 ASDIFS (I) t 11 ASDI (I) THREE-STATE ASDOFS (O) THREE-STATE ASDO (O) NOTE I = INPUT, O = OUTPUT t 12 t 11 t10 D9 D8 t 13 t17 t 16 A1 A0 t 14 D9 t 15 A2 A1 A0 Figure 6. Auxiliary Serial Port ASPORT D9 D8 D7 D9 D8 BSE (I) THREE-STATE BSCLK (O) t 18 BSDIFS (I) t 19 BSDI (I) THREE-STATE BSDOFS (O) t 20 THREE-STATE BSDO (O) NOTE I = INPUT, O = OUTPUT t19 t18 D9 D8 t 21 t 22 D9 t 23 t25 t 24 A1 A0 A2 A1 A0 Figure 7. Baseband Serial Port BSPORT D9 D8 D7 D9 D8 REV. 0 –5– 5 Page AD7729 10 0 –10 –20 –30 –40 –50 –60 –70 –80 –90 –100 –110 –120 0 50 100 150 200 250 300 FREQUENCY – kHz Figure 14. Digital Filter Frequency Response Filter Characteristics The digital filter is a 288-tap FIR filter, clocked at half the mas- ter clock frequency. The 3 dB point is at 96 kHz. Due to the low-pass nature of the receive filters, a settling time is associated with step input functions. Output data will not be meaningful until all the digital filter taps have been loaded with data samples taken after the step change. Hence the AD7729 digital filters have a settling time of 44.7 µs (288 × 2t1). Receive Offset Calibration Included in the digital filter is a means by which receive offsets may be calibrated out. Each channel of the digital low-pass filter section has an offset register. The offset register can be made to contain a value representing the dc offset of the preceding ana- log circuitry. In normal operation, the value stored in the offset register is subtracted from the filter output data before the data appears on the serial output pin. By so doing, dc offsets in the I and Q channels are calibrated out. Autocalibration or user- calibration can be selected. Internal autocalibration will remove internal offsets only while user calibration allows the user to write to the offset register in order to also remove external offsets. The offset registers have enough resolution to hold the value of any dc offset between ± 162.5 mV (1/8th of the input range). Offsets larger than ± 162.5 mV will cause a spurious result due to calibration overrange. However, the performance of the sigma- delta modulators will degrade if full-scale signals with more than 100 mV of offset are experienced. The 10-bit offset register represents a twos complement value. The LSB of the offset registers corresponds to Bit 3 of the Rx words while the MSB of the offset registers corresponds to Bit 12 of the Rx words (see Figure 15). RxDATA 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 OFFSET REGISTER 9 8 7 6 5 4 3 2 1 0 Figure 15. Position of the 10-Bit Offset Word Receive Offset Adjust: Autocalibration If receive autocalibration is selected, the AD7729 will initiate an autocalibration routine each time the receive path is brought out of the low power sleep mode. After RxON is asserted, by taking the RxON bit or the RxON pin high, 36 symbol periods are allowed for the analog and digital circuitry to settle. An internal timer then times out a time equal to RxDELAY1. When RxDELAY1 has expired, the AD7729 offset calibration routine begins, assuming the RxAUTOCAL bit in control regis- ter BCRA is equal to 1. If RxAUTOCAL equals zero, no cali- bration occurs and T2 in Figure 16 equals zero. In internal autocalibration mode, the AD7729 internally disconnects the differential inputs from the input pins and shorts the inputs to measure the resulting ADC offset. In external autocalibration mode, the inputs remain connected to the pins, allowing system offsets along with the AD7729 internal offsets to be evaluated. This is then averaged 16 times to reduce noise and the averaged result is then placed in the offset register. The input to the ADC is then switched back for normal operation and the analog cir- cuitry and digital filter are permitted to settle. This time period is included in TCALIBRATE, which equals 40 × 48 MCLK cycles. RxON T0 T1 T2 T3 T0 = TSETTLE = 36 ؋ 48 MCLKs T1 = RxDELAY1 = 0...255 ؋ 48 MCLKs T2 = TCALIBRATE = 40 ؋ 48 MCLKs T3 = RxDELAY2 = 0...255 ؋ 48 MCLKs FIRST VALID OUTPUT WORD HERE Figure 16. Data Rx Procedure After calibration is complete, a second timer is started which times out a time equal to RxDELAY2. The range of both RxDELAY1 and RxDELAY2 is 0 to 255 units where each unit equals one bit time. Therefore, the maximum delay time is 255 × 1/270 kHz = 941.55 µs. As soon as RxDELAY2 has expired, valid output words appear at the output. The Rx data will be 15 bits wide. ASDOFS BSDOFS ASDO BSDO VALID I DATA I FLAG VALID Q DATA Q FLAG T1 I WORD T2 T1 Q WORD T2 T1 = 16 MCLKs T2 = 8 MCLKs Figure 17. ASDO/BSDO in Rx Mode Receive Offset Adjust: User Calibration When user calibration is selected, the receive offset register can be written to, allowing offsets in the IF/RF demodulation cir- cuitry to be calibrated out also. However, the user is now re- sponsible for calibrating out receive offsets belonging to the AD7729. When the receive path enters the low power mode, the registers remain valid. After powering up, the first IQ sample pair is output once time has elapsed for both the analog circuitry to settle and also for the output of the digital filter to settle. REV. 0 –11– 11 Page

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