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PDF AD7722 Data sheet ( Hoja de datos )
| Número de pieza | AD7722 | |
| Descripción | 16-Bit/ 195 kSPS CMOS/ Sigma-Delta ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
16-Bit, 195 kSPS
CMOS, Sigma-Delta ADC
AD7722
FEATURES
16-Bit Sigma-Delta ADC
64؋ Oversampling Ratio
Up to 220 kSPS Output Word Rate
Low-Pass, Linear Phase Digital Filter
Inherently Monotonic
On-Chip 2.5 V Voltage Reference
Single Supply +5 V
High Speed Parallel or Serial Interface
GENERAL DESCRIPTION
The AD7722 is a complete low power, 16-bit, sigma-delta
ADC. The part operates from a +5 V supply and accepts a
differential input voltage range of 0 V to +2.5 V or ± 1.25 V
centered around a common-mode bias. The AD7722 provides
16-bit performance for input bandwidths up to 90.625 kHz.
The part provides data at an output word rate of 195.3 kHz.
The analog input is continuously sampled by an analog modula-
tor eliminating the need for external sample-and-hold circuitry.
The modulator output is processed by two Finite Impulse
Response (FIR) digital filters in series. The on-chip filtering
reduces the external antialias requirements to first order, in
most cases. The group delay for the filter is 215.5 µs, while the
settling time for a step input is 431 µs. The sample rate, filter
corner frequency, and output word rate are set by an external
clock that is nominally 12.5 MHz.
Use of a single bit DAC in the modulator guarantees excellent
linearity and dc accuracy. Endpoint accuracy is ensured by on-
chip calibration. This calibration procedure minimizes the zero-
scale and full-scale errors.
FUNCTIONAL BLOCK DIAGRAM
DGND DVDD AGND AVDD REF1
VIN(+)
VIN(–)
P/S
CAL
RESET
SYNC
CS
DVAL/RD
CFMT/DRDY
DB0
DB1
DB2
AD7722
2.5V
REFERENCE
16-BIT A/D CONVERTER
Σ∆ FIR
MODULATOR FILTER
CLOCK
CIRCUITRY
CONTROL
LOGIC
REF2
XTAL
CLKIN
UNI
DB15
DB14
DB13
DB12
DB11
DB10
DB9/FSO
DB3/ DB4/ DB5/ DB6/ DB7/ DB8/
TSI DOE SFMT FSI SCO SDO
Conversion data is provided at the output register through a
flexible serial port or a parallel port. This offers 3-wire, high
speed interfacing to digital signal processors. The serial interface
operates in an internal clocking (master) mode, whereby an
internal serial data clock and framing pulse are device outputs.
Additionally, two AD7722s can be configured with the serial
data outputs connected together. Each converter alternately
transmits its conversion data on a shared serial data line.
The part provides an accurate on-chip 2.5 V reference. A
reference input/output function is provided to allow either the
internal reference or an external system reference to be used as
the reference source for the part.
The AD7722 is available in a 44-pin PQFP package and is
specified over the industrial temperature range from –40°C to
+85°C.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700 World Wide Web Site: http://www.analog.com
Fax: 617/326-8703
© Analog Devices, Inc., 1996
1 page  
REV. 0
CLKIN
SCO
(CFMT = 0)
FSO
(SFMT = 0)
64 CKLIN CYCLES
32 SCO CYCLES
AD7722
SCO
VALID DATA FOR 16 SCO CYCLES
ZERO FOR LAST 16 SCO CYCLES VALID
Figure 2a. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
CLKIN
64 CKLIN CYCLES
SCO
(CFMT = 0)
FSO
(SFMT = 1)
SCO
32 SCO CYCLES
LOW FOR 16 SCO CYCLES
VALID DATA FOR 16 SCO CYCLES
HIGH FOR LAST 16 SCO CYCLES
ZERO FOR LAST 16 SCO CYCLES VALID
Figure 2b. Generalized Serial Mode Timing (FSI = Logic Low or High, TSI = DOE)
CLKIN
FSI
SCO
2.3V
t5
0.8V
t1
t6
t9
t4
t9
t 10
t8
t7
t2
t3
Figure 3. Serial Mode Timing for Clock Input, Frame Sync Input and Serial Clock Output
CLKIN
FSI
SCO
SFMT = LOGIC FSO
LOW(0)
SDO
t1
t 10
t11 t12
t 14
D15
t 13
D14
SCO
SFMT = LOGIC FSO
HIGH(1)
LOW FOR
D15–D0
t 12
t 13
SDO
D15 D14 D13
D13
D1
D1
t 11
D0
D0
Figure 4. Serial Mode Timing for Frame Sync Input, Frame Sync Output, Serial Clock Output
and Serial Data Output (CFMT = Logic Low, TSI = DOE)
–5–
5 Page 
Typical Characteristics–AD7722
(AVDD = DVDD = 5.0 V, TA = +25؇C; CLKIN = 12.5 MHz, AIN = 20 kHz, Bipolar Mode; VIN(+) = 0 V to 2.5 V, VIN(–) = 1.25 V unless otherwise noted)
110
100
90
80
70
60
50
–40
SFDR
S/ (N+D)
–30 –20
–10
INPUT LEVEL – dB
0
84
85
AIN = 1/5 · BW
86
87
88
89
90
91
92
0 50 100 150 200 250 300
OUTPUT DATA RATE – kSPS
–85
–90
–95
–100
–105
–110
–115
0
SNR
SFDR
THD
20 40 60 80
INPUT FREQUENCY – kHz
100
Figure 9. S/(N+D) and SFDR vs.
Analog Input Level
Figure 10. S/(N+D) vs. Output
Sample Rate
Figure 11. SNR, THD, and SFDR vs.
Input Frequency
–85
–90
SNR
–95
–100 THD
VIN (+) = VIN(–) = 1.25Vpk–pk
VCM = 2.5V
–105
SFDR
–110
–115
0
20 40 60 80
INPUT FREQUENCY – kHz
100
Figure 12. SNR, THD, and SFDR vs.
Input Frequency
84
85
AIN = 1/5 · BW
86 VIN (+) = VIN(–) = 1.25Vpk–pk
VCM = 2.5V
87
88
89
90
91
92
0
50 100 150 200 250 300
OUTPUT DATA RATE – kSPS
Figure 13. S/(N+D) vs. Output
Sample Rate
92.0
91.5
91.0
90.5
90.0
89.5
89.0
88.5
88.0
–50
0 50
TEMPERATURE – °C
100
Figure 14. SNR vs. Temperature
–94
–96
–98
–100
–102
–104
–106
–108
–110
–112
–114
–116
–50
THD
3RD
4TH
2ND
–25 0 25 50 75
TEMPERATURE – °C
100
Figure 15. THD vs. Temperature
5000
4500
4000
3500
3000
2500
2000
1500
1000
500
0
n–3
n–2
VIN(+) = VIN(–)
CLKIN = 12.5MHz
8k SAMPLES
n–1 n n+1 n+2 n+3
CODES
Figure 16. Histogram of Output
Codes with DC Input
1.0
0.8
0.6
0.4
0.2
0
–0.2
–0.4
–0.6
–0.8
–1.0
0
20000
40000
CODE
65535
Figure 17. Differential Nonlinearity
REV. 0
–11–
11 Page | ||
| Páginas | Total 24 Páginas | |
| PDF Descargar | [ Datasheet AD7722.PDF ] | |
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