|
|
PDF AD7716 Data sheet ( Hoja de datos )
| Número de pieza | AD7716 | |
| Descripción | LC2MOS 22-Bit Data Acquisition System | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7716 (archivo pdf) en la parte inferior de esta página. Total 16 Páginas | ||
|
No Preview Available !
a
FEATURES
22-Bit Sigma-Delta ADC
Dynamic Range of 105 dB (146 Hz Input)
؎0.003% Integral Nonlinearity
On-Chip Low-Pass Digital Filter
Cutoff Programmable from 584 Hz to 36.5 Hz
Linear Phase Response
Five Line Serial I/O
Twos Complement Coding
Easy Interface to DSPs and Microcomputers
Software Control of Filter Cutoff
؎5 V Supply
Low Power Operation: 50 mW
APPLICATIONS
Biomedical Data Acquisition
ECG Machines
EEG Machines
Process Control
High Accuracy Instrumentation
Seismic Systems
LC2MOS
22-Bit Data Acquisition System
AD7716
FUNCTIONAL BLOCK DIAGRAM
AVDD DVDD AVSS RESET A0 A1 A2 CLKIN CLKOUT
AIN 1
AD7716
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
AIN 2
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
AIN 3
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
AIN 4
ANALOG
MODULATOR
LOW PASS
DIGITAL
FILTER
CLOCK
GENERATION
CONTROL
LOGIC
OUTPUT
SHIFT
REGISTER
CONTROL
REGISTER
MODE
CASCIN
CASCOUT
RFS
SDATA
SCLK
DRDY
TFS
VREF AGND DGND
DIN 1 DOUT1 DOUT2
GENERAL DESCRIPTION
The AD7716 is a signal processing block for data acquisition
systems. It is capable of processing four channels with band-
widths of up to 584 Hz. Resolution is 22 bits and the usable
dynamic range varies from 111 dB with an input bandwidth of
36.5 Hz to 99 dB with an input bandwidth of 584 Hz.
The device consists of four separate A/D converter channels that
are implemented using sigma-delta technology. Sigma-delta
ADCs include on-chip digital filtering and, thus, the system
filtering requirements are eased.
Three address pins program the device address. This allows a
data acquisition system with up to 32 channels to be set up in a
simple fashion. The output word from the device contains 32
bits of data. One bit is determined by the state of the DIN1 in-
put and may be used, for example, in an ECG system with an
external pacemaker detect circuit to indicate that the output
word is invalid because of the presence of a pacemaker pulse.
There are 22 bits of data corresponding to the analog input.
Two bits contain the channel address and 3 bits are the device
address. Thus, each channel in a 32-channel system would have
a discrete 5-bit address. The device also has a CASCOUT pin
and a CASCIN pin that allow simple networking of multiple
devices.
The on-chip control register is programmed using the SCLK,
SDATA and TFS pins. Three bits of the Control Register set
the digital filter cutoff frequency for the device. Selectable fre-
quencies are 584 Hz, 292 Hz, 146 Hz, 73 Hz and 36.5 Hz. A
further 2 bits appear as outputs DOUT1 and DOUT2 and can be
used for controlling calibration at the front end. The device is
available in a 44-pin PQFP (Plastic Quad Flatpack) and 44-pin
PLCC.
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7716
SLAVE MODE TIMING CHARACTERISTICS1, 2 (AVDD= DVDD = +5 V ؎ 5%; AVSS = –5 V ؎ 5%; AGND = DGND = 0 V;
fCLKIN = 8 MHz; Input Levels: Logic 0 = 0 V, Logic 1 = DVDD; unless otherwise noted)
Parameter
(B Version)
Units
Conditions/Comments
fCLKIN3, 4
tr5
tf5
t23
t24
t25
t26
t27
t286
t29
t307
t31
t32
400
8
40
40
1/fCLKIN
50
125
1/fCLKIN +30
30
50
50
50
0
60
2/fCLKIN
kHz min
MHz max
ns max
ns max
ns min
ns min
ns min
ns min
ns min
ns max
ns min
ns max
ns min
ns max
ns max
CLKIN Frequency
Digital Output Rise Time. Typically 20 ns
Digital Output Fall Time. Typically 20 ns
CASCIN Pulse Width
SCLK Width
SCLK Period
CASCIN High to RFS Setup Time
RFS Low to SCLK High Setup Time
SCLK High to SDATA Valid Delay
RFS Hold Time After SCLK High
SCLK High to SDATA High Impedance Delay
SCLK High to CASCOUT High Delay.
CASCOUT Pulse Width
NOTES
1Sample tested at +25°C to ensure compliance. All input signals are specified with tr = tf = 5 ns (10% to 90% of 5 V) and timed from a voltage level of 1.6 V.
2See Figures 1 and 4.
3CLKIN duty cycle range is 40% to 60%.
4The AD7716 is production tested with fCLKIN at 8 MHz in the slave mode. It is guaranteed by characterization to operate at 400 kHz.
5Specified using 10% and 90% points on waveform of interest.
6t28 is measured with the load circuit of Figure 1 and defined as the time required for an output to cross 0.8 V or 2.4 V.
7t30 is derived from the measured time taken by the data outputs to change 0.5 V when loaded with the circuit of Figure 1. The measured number is then extrapolated
back to remove the effects of charging or discharging the 100 pF capacitor. This means that the time quoted in the timing characteristics is the true bus relinquish
time of the part and as such is independent of external bus loading capacitances.
CASCIN (I)
SCLK (I)
RFS (I)
SDATA (O)
CASCOUT (O)
t23
t 26
t 24
t 24
t 27
t25
t29
t28 t30
DB31
CH1
DB30
CH1
DB29
CH1
DB28 DB27 DB2
CH1 CH1 CH4
DB1
CH4
DB0
CH4
t31 t32
Figure 4. Slave Mode Timing Diagram
REV. A
–5–
5 Page 
AD7716
Source Resistance
If passive attenuators are used in front of the AD7716, care
must be taken to ensure that the source impedance is suffi-
ciently low. The dc input resistance for the AD7716 is greater
than 1 GΩ. In parallel with this there is a small sampling ca-
pacitor. The dynamic load presented by this varies with the
clock frequency. The modulator sampling rate determines the
amount of time available for the sampling capacitor to be
charged. Any extra external impedances result in a longer over-
all charge time resulting in extra gain errors on the analog input.
The AD7716 has a quite large gain error (1% FSR) due to the
fact that there is no on-chip calibration. Thus, even an extra
10 kΩ source resistance and 50 pF source capacitance will have
no significant effect on this.
Active signal conditioning circuits such as op amps generally do
not suffer from problems of high source impedance. Their
open-loop output resistance is normally only tens of ohms and,
in any case, most modern general purpose op amps have
sufficiently fast closed-loop settling time for this not to be a
problem.
Accuracy
Sigma-delta ADCs, like VFCs and other integrating ADCs, do
not contain any source of nonmonotonicity and inherently offer
no missing codes performance.
The AD7716 achieves excellent linearity by the use of high
quality, on-chip silicon dioxide capacitors, which have a very
low capacitance/voltage coefficient.
Drift Considerations
The AD7716 uses autozeroing techniques to minimize input
offset drift. Charge injection in the analog switches and leakage
currents at the sampling node are the primary sources of offset
voltage drift in the converter. Figure 7 indicates the typical off-
set due to temperature changes. Drift is relatively flat up to
85°C. Above this temperature, leakage current becomes the
main source of offset drift. Since leakage current doubles ap-
proximately every 10°C, the offset drifts accordingly. The value
of the voltage on the sample capacitor is updated at a rate deter-
mined by the master clock, therefore the amount of offset drift
which occurs will be proportional to the elapsed time between
samples.
Gain drift within the converter depends mainly upon the tem-
perature tracking of the internal capacitors. It is not affected by
leakage currents.
–0.125
–0.25
–0.375
–0.500
–0.625
20 30 40 50 60 70 80 90
TEMPERATURE – °C
Figure 7. Typical Offset Drift
Voltage Reference
The voltage applied to the VREF pin defines the analog input
range. The specified reference voltage is 2.5 V ± 10%.
The reference input presents exactly the same dynamic load as
the analog input, but in the case of the reference input, source
resistance and long settling time introduce gain errors rather
than offset errors. Most precision references however have suffi-
ciently low output impedance and wide enough bandwidth to
settle to the required accuracy in the time allowed by the
AD7716.
The reference should be chosen to have minimal noise in the
programmed passband. Recommended references are the
AD780 or the REF43 from Analog Devices. These low noise
references have typical noise spectral densities of 100 nV/√Hz at
600 Hz. This corresponds to an rms noise of 2.5 µV in this
band and is more than adequate for the AD7716.
Clock Generation
The device operates from a master clock which must be pro-
vided either from a crystal source or an external clock source. If
a crystal is used, it must be connected across the CLKIN and
CLKOUT pins. Typical loading capacitors of 15 pF are re-
quired on CLKIN, CLKOUT. The crystal manufacturers data
should be consulted for more information. An external clock
can also be used to drive the CLKIN input directly with a
CMOS compatible clock. In this case, CLKOUT is left uncon-
nected. The nominal clock frequency for the device is 8 MHz.
REV. A
–11–
11 Page | ||
| Páginas | Total 16 Páginas | |
| PDF Descargar | [ Datasheet AD7716.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7710 | Signal Conditioning ADC | Analog Devices |
| AD7711 | LC2MOS Signal Conditioning ADC with RTD Excitation Currents | Analog Devices |
| AD7712 | LC2MOS Signal Conditioning ADC | Analog Devices |
| AD7713 | LC2MOS Loop-Powered Signal Conditioning ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |