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PDF AD7678 Data sheet ( Hoja de datos )
| Número de pieza | AD7678 | |
| Descripción | 18-Bit/ 2.5 LSB INL/ 570 kSPS SAR ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD7678 (archivo pdf) en la parte inferior de esta página. Total 28 Páginas | ||
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18-Bit, 2.5 LSB INL, 570 kSPS SAR ADC
AD7679
FEATURES
18-bit resolution with no missing codes
No pipeline delay (SAR architecture)
Differential input range: ±VREF (VREF up to 5 V)
Throughput: 570 kSPS
INL: ±2.5 LSB max (±9.5 ppm of full scale)
Dynamic range : 103 dB typ (VREF = 5 V)
S/(N+D): 100 dB typ @ 2 kHz (VREF = 5 V)
Parallel (18-,16-, or 8-bit bus) and serial 5 V/3 V interface
SPI®/QSPI™/MICROWIRE™/DSP compatible
On-board reference buffer
Single 5 V supply operation
Power dissipation: 76 mW @ 500 kSPS
150 µW @ 1 kSPS
48-lead LQFP or 48-lead LFCSP package
Pin-to-pin compatible upgrade of AD7674/AD7676/AD7678
APPLICATIONS
CT scanners
High dynamic data acquisition
Geophone and hydrophone sensors
Σ-∆ replacement (low power, multichannel)
Instrumentation
Spectrum analysis
Medical instruments
GENERAL DESCRIPTION
The AD7679 is an 18-bit, 570 kSPS, charge redistribution SAR,
fully differential analog-to-digital converter that operates on a
single 5 V power supply. The part contains a high speed 18-bit
sampling ADC, an internal conversion clock, an internal
reference buffer, error correction circuits, and both serial and
parallel system interface ports.
The part is available in a 48-lead LQFP or 48-lead LFCSP with
operation specified from –40°C to +85°C.
FUNCTIONAL BLOCK DIAGRAM
PDBUF REF REFGND
DVDD DGND
AGND
AVDD
REFBUFIN
AD7679
SERIAL
PORT
OVDD
OGND
IN+
IN–
PD
RESET
SWITCHED
CAP DAC
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
18
PARALLEL
INTERFACE
D[17:0]
BUSY
RD
CS
MODE0
MODE1
CNVST
Figure 1. Functional Block Diagram
03085–0–001
Table 1. PulSAR Selection
Type/kSPS
Pseudo-
Differential
True Bipolar
True
Differential
18-Bit
Multichannel/
Simultaneous
100–250
AD7651
AD7660/AD7661
AD7663
AD7675
AD7678
500–570
AD7650/AD7652
AD7664/AD7666
AD7665
AD7676
AD7679
AD7654
AD7655
800–
1000
AD7653
AD7667
AD7671
AD7677
AD7674
PRODUCT HIGHLIGHTS
1. High Resolution, Fast Throughput.
The AD7679 is a 570 kSPS, charge redistribution, 18-bit
SAR ADC (no latency).
2. Excellent Accuracy.
The AD7679 has a maximum integral nonlinearity of
2.5 LSB with no missing 18-bit codes.
3. Serial or Parallel Interface.
Versatile parallel (18-, 16-, or 8-bit bus) or 3-wire serial
interface arrangement compatible with both 3 V and
5 V logic.
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable.
However, no responsibility is assumed by Analog Devices for its use, nor for any
infringements of patents or other rights of third parties that may result from its use.
Specifications subject to change without notice. No license is granted by implication
or otherwise under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective companies.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.326.8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD7679
TIMING SPECIFICATIONS
Table 3. –40°C to +85°C, AVDD = DVDD = 5 V, OVDD = 2.7 V to 5.25 V, unless otherwise noted.
Parameter
Symbol Min
Refer to Figure 32 and Figure 33
Convert Pulsewidth
Time between Conversions
CNVST LOW to BUSY HIGH Delay
t1 10
t2 1.75
t3
BUSY HIGH All Modes Except Master Serial Read after Convert
Aperture Delay
End of Conversion to BUSY LOW Delay
Conversion Time
Acquisition Time
RESET Pulsewidth
Refer to Figure 34, Figure 35, and Figure 36 (Parallel Interface Modes)
CNVST LOW to Data Valid Delay
t4
t5
t6 10
t7
t8 250
t9 10
t10
Data Valid to BUSY LOW Delay
Bus Access Request to Data Valid
Bus Relinquish Time
Refer to Figure 38 and Figure 39 (Master Serial Interface Modes) 1
CS LOW to SYNC Valid Delay
t11 20
t12
t13 5
t14
CS LOW to Internal SCLK Valid Delay
t15
CS LOW to SDOUT Delay
t16
CNVST LOW to SYNC Delay
SYNC Asserted to SCLK First Edge Delay2
Internal SCLK Period2
Internal SCLK HIGH2
Internal SCLK LOW2
SDOUT Valid Setup Time2
SDOUT Valid Hold Time2
SCLK Last Edge to SYNC Delay2
CS HIGH to SYNC HI-Z
t17
t18 3
t19 25
t20 12
t21 7
t22 4
t23 2
t24 3
t25
CS HIGH to Internal SCLK HI-Z
t26
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read after Convert2
CNVST LOW to SYNC Asserted Delay
SYNC Deasserted to BUSY LOW Delay
Refer to Figure 40 and Figure 41 (Slave Serial Interface Modes)
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t27
t28
t29
t30
t31 5
t32 3
t33 5
t34 5
t35 25
t36 10
t37 10
Typ
2
525
See Table 4
1.5
25
Max Unit
ns
µs
35 ns
1.5 µs
ns
ns
1.5 µs
ns
ns
1.5 µs
ns
45 ns
15 ns
10 ns
10 ns
10 ns
ns
ns
40 ns
ns
ns
ns
ns
ns
10 ns
10 ns
10 ns
µs
ns
ns
18 ns
ns
ns
ns
ns
ns
1In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load CL of 10 pF; otherwise, the load is 60 pF maximum.
2In Serial Master Read during Convert mode. See Table 4 for Serial Master Read after Convert mode.
Rev. 0 | Page 5 of 28
5 Page 
DEFINITION OF SPECIFICATIONS
Integral Nonlinearity Error (INL)
Linearity error refers to the deviation of each individual code
from a line drawn from negative full scale through positive full
scale. The point used as negative full scale occurs ½ LSB before
the first code transition. Positive full scale is defined as a level
1½ LSB beyond the last code transition. The deviation is
measured from the middle of each code to the true straight line.
Differential Nonlinearity Error (DNL)
In an ideal ADC, code transitions are 1 LSB apart. Differential
nonlinearity is the maximum deviation from this ideal value. It
is often specified in terms of resolution for which no missing
codes are guaranteed.
Gain Error
The first transition (from 000…00 to 000…01) should occur for
an analog voltage ½ LSB above the nominal –full scale
(–4.095991 V for the ±4.096 V range). The last transition (from
111…10 to 111…11) should occur for an analog voltage
1½ LSB below the nominal full scale (4.095977 V for the
±4.096 V range). The gain error is the deviation of the
difference between the actual level of the last transition and the
actual level of the first transition from the difference between
the ideal levels.
Zero Error
The zero error is the difference between the ideal midscale
input voltage (0 V) from the actual voltage producing the
midscale output code.
Spurious-Free Dynamic Range (SFDR)
SFDR is the difference, in decibels (dB), between the rms
amplitude of the input signal and the peak spurious signal.
Effective Number of Bits (ENOB)
ENOB is a measurement of the resolution with a sine wave
input, and is expressed in bits. It is related to S/(N+D) by the
following formula:
ENOB = (S/[N+D]dB – 1.76)/6.02
AD7679
Total Harmonic Distortion (THD)
THD is the ratio of the rms sum of the first five harmonic
components to the rms value of a full-scale input signal, and is
expressed in decibels.
Dynamic Range
Dynamic range is the ratio of the rms value of the full scale to
the rms noise measured with the inputs shorted together. The
value for dynamic range is expressed in decibels.
Signal-to-Noise Ratio (SNR)
SNR is the ratio of the rms value of the actual input signal to the
rms sum of all other spectral components below the Nyquist
frequency, excluding harmonics and dc. The value for SNR is
expressed in decibels.
Signal-to-(Noise + Distortion) Ratio (S/[N+D])
S/(N+D) is the ratio of the rms value of the actual input signal
to the rms sum of all other spectral components below the
Nyquist frequency, including harmonics but excluding dc. The
value for S/(N+D) is expressed in decibels.
Aperture Delay
Aperture delay is a measure of the acquisition performance and
is measured from the falling edge of the CNVST input to when
the input signal is held for a conversion.
Transient Response
Transient response is the time required for the AD7679 to
achieve its rated accuracy after a full-scale step function is
applied to its input.
Rev. 0 | Page 11 of 28
11 Page | ||
| Páginas | Total 28 Páginas | |
| PDF Descargar | [ Datasheet AD7678.PDF ] | |
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