|
|
PDF AD7650 Data sheet ( Hoja de datos )
| Número de pieza | AD7650 | |
| Descripción | Low Cost CMOS ADC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
|
Hay una vista previa y un enlace de descarga de AD7650 (archivo pdf) en la parte inferior de esta página. Total 21 Páginas | ||
|
No Preview Available !
a
FEATURES
Throughput
570 kSPS (Warp Mode)
500 kSPS (Normal Mode)
16 Bits Resolution
Analog Input Voltage Range: 0 V to 2.5 V
No Pipeline Delay
Parallel and Serial 5 V/3 V Interface
SPI™/QSPI™/MICROWIRE™/DSP Compatible
Single 5 V Supply Operation
Power Dissipation
77 mW Typical @ 444 kSPS (Impulse Mode)
21 W @ 100 SPS
Power-Down Mode: 7 W Max
Package: 48-Lead Quad Flat Pack (LQFP) or 48-Lead
Frame Chip-Scale Pack (LFCSP)
Pin-to-Pin Compatible with PulSAR ADCs
APPLICATIONS
Data Acquisition
Instrumentation
Digital Signal Processing
Spectrum Analysis
Medical Instruments
Battery-Powered Systems
Process Control
16-Bit, 570 kSPS
Low Cost CMOS ADC
AD7650
FUNCTIONAL BLOCK DIAGRAM
AVDD AGND REF REFGND
DVDD DGND
IN+
IN–
PD
RESET
AD7650
SWITCHED
CAP DAC
SERIAL
PORT
CLOCK
CONTROL LOGIC AND
CALIBRATION CIRCUITRY
PARALLEL 16
INTERFACE
OVDD
OGND
SER/PAR
BUSY
DATA[15:0]
CS
RD
OB/2C
WARP IMPULSE CNVST
GENERAL DESCRIPTION
The AD7650 is a 16-bit, 570 kSPS, charge redistribution SAR,
analog-to-digital converter that operates from a single 5 V power
supply. The part contains a high-speed 16-bit sampling ADC,
an internal conversion clock, error correction circuits, and both
serial and parallel system interface ports.
It features a very high sampling rate mode (Warp) and, for
asynchronous conversion rate applications, a fast mode (Normal)
and, for low power applications, a reduced power mode (Impulse)
where the power is scaled with the throughput.
It is fabricated using Analog Devices’ high-performance,
0.6 micron CMOS process and is available in a 48-lead LQFP
or in a tiny 48-lead Chip Scale package with operation specified
from –40°C to +85°C.
PRODUCT HIGHLIGHTS
1. Fast Throughput
The AD7650 is a 570 kSPS, charge redistribution, 16-bit
SAR ADC.
2. Single-Supply Operation
The AD7650 operates from a single 5 V supply. In impulse
mode, its power dissipation decreases with the throughput from
77 mW at 444 kSPS throughput to, for instance, only 21 µW
at a 100 SPS throughput. It consumes 7 µW maximum when
in power-down.
3. Serial or Parallel Interface
Versatile parallel or 2-wire serial interface arrangement com-
patible with both 3 V or 5 V logic.
SPI and QSPI are trademarks of Motorola, Inc.
MICROWIRE is a trademark of National Semiconductor Corporation.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 2002
1 page  
AD7650
TIMING SPECIFICATIONS (continued)
Parameter
Symbol
Min
Typ
Max
Unit
REFER TO FIGURES 13 AND 14 (continued)
SCLK Last Edge to SYNC Delay
CS HIGH to SYNC HI-Z
CS HIGH to Internal SCLK HI-Z
CS HIGH to SDOUT HI-Z
BUSY HIGH in Master Serial Read After Convert
(Warp Mode/Normal Mode/Impulse Mode)
t24
t25
t26
t27
t28
3
10
10
10
2.75/3/3.25
CNVST LOW to SYNC Asserted Delay
(Warp Mode/Normal Mode/Impulse Mode)
t29
1/1.25/1.5
SYNC Deasserted to BUSY LOW Delay
t30
50
REFER TO FIGURES 15 AND 16
(Slave Serial Interface Modes)2
External SCLK Setup Time
External SCLK Active Edge to SDOUT Delay
SDIN Setup Time
SDIN Hold Time
External SCLK Period
External SCLK HIGH
External SCLK LOW
t31
t32
t33
t34
t35
t36
t37
5
3
5
5
25
10
10
16
NOTES
1In warp mode only, the maximum time between conversions is 1 ms; otherwise, there is no required maximum time.
2In serial interface modes, the SYNC, SCLK, and SDOUT timings are defined with a maximum load C L of 10 pF; otherwise, the load is 60 pF maximum.
3If the polarity of SCLK is inverted, the timing references of SCLK are also inverted.
Specifications subject to change without notice.
ns
ns
ns
µs
µs
ns
ns
ns
ns
ns
ns
ns
ns
1.6mA IOL
TO OUTPUT
PIN
CL
60pF*
500A IOH
1.4V
*IN SERIAL INTERFACE MODES,THE SYNC, SCLK, AND
SDOUT TIMINGS ARE DEFINED WITH A MAXIMUM LOAD
CL OF 10pF; OTHERWISE,THE LOAD IS 60pF MAXIMUM.
Figure 1. Load Circuit for Digital Interface Timing,
SDOUT, SYNC, SCLK Outputs, CL = 10 pF
0.8V
tDELAY
2V
0.8V
2V
tDELAY
2V
0.8V
Figure 2. Voltage Reference Levels for Timing
–4– REV. 0
5 Page 
AD7650
CIRCUIT INFORMATION
The AD7650 is a very fast, low power, single supply, precise
16-bit analog-to-digital converter (ADC). The AD7650 features
different modes to optimize performances according to the
applications.
In warp mode, the AD7650 is capable of converting 570,000
samples per second (570 kSPS).
The AD7650 provides the user with an on-chip track/hold,
successive approximation ADC that does not exhibit any pipe-
line or latency, making it ideal for multiple multiplexed channel
applications.
The AD7650 can be operated from a single 5 V supply and be
interfaced to either 5 V or 3 V digital logic. It is housed in 48-lead
LQFP or in a tiny 48-LFCSP packages that save space and allows
flexible configurations as either serial or parallel interface. The
AD7650 is pin-to-pin compatible with the AD7664.
CONVERTER OPERATION
The AD7650 is a successive-approximation analog-to-digital
converter based on a charge redistribution DAC. Figure 3 shows
the simplified schematic of the ADC. The capacitive DAC consists
of an array of 16 binary weighted capacitors and an additional
“LSB” capacitor. The comparator’s negative input is connected to
a “dummy” capacitor of the same value as the capacitive DAC array.
During the acquisition phase, the common terminal of the array
tied to the comparator’s positive input is connected to AGND via
SWA. All independent switches are connected to the analog input
IN+. Thus, the capacitor array is used as a sampling capacitor
and acquires the analog signal on IN+ input. Similarly, the
“dummy” capacitor acquires the analog signal on IN– input.
When the CNVST input goes low, a conversion phase is initiated.
When the conversion phase begins, SWA and SWB are opened
first. The capacitor array and the “dummy” capacitor are then
disconnected from the inputs and connected to the REFGND
input. Therefore, the differential voltage between IN+ and
IN– captured at the end of the acquisition phase is applied to
the comparator inputs, causing the comparator to become unbal-
anced. By switching each element of the capacitor array between
REFGND or REF, the comparator input varies by binary-
weighted voltage steps (VREF /2, VREF /4, . . . VREF /65536). The
control logic toggles these switches, starting with the MSB first,
to bring the comparator back into a balanced condition. After
the completion of this process, the control logic generates the
ADC output code and brings BUSY output low.
Modes of Operation
The AD7650 features three modes of operations, Warp, Normal,
and Impulse. Each of these modes is more suitable for specific
applications.
The Warp mode allows the fastest conversion rate up to 570 kSPS.
However, in this mode, and this mode only, the full specified
accuracy is guaranteed only when the time between conversion
does not exceed 1 ms. If the time between two consecutive
conversions is longer than 1 ms, for instance, after power-up,
the first conversion result should be ignored. This mode makes
the AD7650 ideal for applications where both high accuracy and
fast sample rate are required.
The normal mode is the fastest mode (500 kSPS) without any
limitation about the time between conversions. This mode makes the
AD7650 ideal for asynchronous applications such as data acqui-
sition systems, where both high accuracy and fast sample rate are
required. It is selected when both IMPULSE and WARP are low.
The impulse mode, the lowest power dissipation mode, allows
power saving between conversions. When operating at 100 SPS,
for example, it typically consumes only 21 µW. This feature
makes the AD7650 ideal for battery-powered applications.
IN+
REF
REFGND
IN–
MSB
32,768C 16,384C
LSB SWA
SWITCHES
CONTROL
4C 2C
CC
65,536C
COMP
SWB
CONTROL
LOGIC
BUSY
OUTPUT
CODE
CNVST
Figure 3. ADC Simplified Schematic
–10–
REV. 0
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD7650.PDF ] | |
Hoja de datos destacado
| Número de pieza | Descripción | Fabricantes |
| AD7650 | Low Cost CMOS ADC | Analog Devices |
| AD7651 | Unipolar ADC | Analog Devices |
| AD7652 | Unipolar ADC | Analog Devices |
| AD7653 | 16-Bit 1 MSPS SAR Unipolar ADC | Analog Devices |
| Número de pieza | Descripción | Fabricantes |
| SLA6805M | High Voltage 3 phase Motor Driver IC. |
 Sanken |
| SDC1742 | 12- and 14-Bit Hybrid Synchro / Resolver-to-Digital Converters. |
Analog Devices |
|
DataSheet.es es una pagina web que funciona como un repositorio de manuales o hoja de datos de muchos de los productos más populares, |
| DataSheet.es | 2020 | Privacy Policy | Contacto | Buscar |