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PDF AD760 Data sheet ( Hoja de datos )
| Número de pieza | AD760 | |
| Descripción | 16/18-Bit Self-Calibrating Serial/Byte DACPORT | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
16/18-Bit Self-Calibrating
Serial/Byte DACPORT
AD760
FEATURES
±0.2 LSB (±0.00031%) Typ Peak DNL and INL
±0.5 LSB (±0.00076%) Typ Unipolar Offset, Bipolar Zero
17-Bit Monotonicity Guaranteed
18-Bit Resolution (in Serial Mode)
Complete 16/18-Bit D/A Function
On-Chip Output Amplifier
On-Chip Buried Zener Voltage Reference
Microprocessor Compatible
Serial or Byte Input
Double Buffered Latches
Asynchronous Clear Function
Serial Output Pin Facilitates Daisy Chaining
Pin Strappable Unipolar or Bipolar Output
Low THD+N: 0.005%
MUX Output Control on Power-Up and Supply Glitches
PRODUCT DESCRIPTION
The AD760 is a complete 16/18-bit self-calibrating monolithic
DAC (DACPORT®) with onboard voltage reference, double
buffered latches and output amplifier. It is manufactured on
Analog Devices’ BiMOS II process. This process allows the fab-
rication of low power CMOS logic functions on the same chip
as high precision bipolar linear circuitry.
Self-calibration is initiated by simply pulsing the CAL pin low.
The CALOK pin indicates when calibration has been success-
fully completed. The output multiplexer (MUXOUT) can be used
to send the output to the bottom of the output range during
calibration.
Data can be loaded into the AD760 as straight binary, serial
data or as two 8-bit bytes. In serial mode, 16-bit or 18-bit data
can be used and the serial mode input format is pin selectable,
to be MSB or LSB first. This is made possible by three digital
input pins which have dual functions (Pins 12, 13, and 14). In
byte mode the user can similarly define whether the high byte or
low byte is loaded first. The serial output (SOUT) pin allows the
user to daisy chain several AD760s by shifting the data through
the input latch into the next DAC thus minimizing the number
of control lines required in a multiple DAC application. The
double buffered latch structure eliminates data skew errors and
provides for simultaneous updating of DACs in a multi-DAC
system.
The asynchronous CLR function can be configured to clear the
output to minus full-scale or midscale depending on the state of
Pin 17 when CLR is strobed. The AD760 also powers up with the
FUNCTIONAL BLOCK DIAGRAM
UNI/
BIP CLR 17
OR LBE
HBE 18
SER 19
CLR 20
LDAC 21
REF IN 25
MSB/ 18/16
SIN LSB SERIAL
OR OR OR
CS DB0 DB1 DB2
DB7
16 14 13 12
7
AD760
16/18-BIT
INPUT REGISTER
10k
16/18-BIT DAC LATCH
10k
9.95k
MAIN DAC
RAM
REF OUT 26 +10V
REF
CALIBRATION DAC
15 SOUT
24 SPAN/
BIP
OFF
23 VOUT
27 MUXOUT
28 MUXIN
22 AGND
CALIBRATION SEQUENCER
1
CALOK
2
CAL
3
–VEE
4
+VCC
5
+VLL
6
DGND
MUX output in a predetermined state by means of a digital and
analog power supply detection circuit. This is particularly use-
ful for robotic and industrial control applications.
The AD760 is available in a 28-pin, 600 mil cerdip package.
The AQ version is specified from –40°C to +85°C.
0.75
VOUT = –10V TO +10V
RL = 2kΩ
CL = 1000pF
0.25
0
–0.25
–0.75
0
16384
32768
49152
INPUT CODE – Decimal
Typical Integral Nonlinearity
65535
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
DACPORT is a registered trademark of Analog Devices, Inc.
© Analog Devices, Inc., 1995
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
CLR
UNI/BIP
CLR
CAL
CALOK
HBE
tCLR
tSET
"1"= BIP, "0"= UNI
tHOLD
Figure 1c. Asynchronous Clear to Bipolar or Unipolar Zero
tCAL
tBUSY
tCD
tCS
tCV
Figure 1d. Calibration Timing
AD760
ABSOLUTE MAXIMUM RATINGS*
VCC to AGND . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +17.0 V
VEE to AGND . . . . . . . . . . . . . . . . . . . . . . . +0.3 V to –17.0 V
VLL to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –0.3 V to +7 V
AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±1 V
Digital Inputs (Pins 2, 7–14, and 16–21)
to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . –1.0 V to +7.0 V
REF IN to AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . ±10.5 V
Span/Bipolar Offset to AGND . . . . . . . . . . . . . . . . . . . ±10.5 V
REF OUT, VOUT, MUXOUT, MUXIN . . . . . Indefinite Short to
AGND, DGND, VCC, VEE, and VLL
θJA, Thermal Impedance . . . . . . . . . . . . . . . . . . . . . . . 50°C/W
Junction Temperature . . . . . . . . . . . . . . . . . . . . . . . . . . 175°C
Storage Temperature . . . . . . . . . . . . . . . . . . –65°C to +150°C
Lead Temperature (Soldering, 10 sec) . . . . . . . . . . . . . +300°C
*Stresses above those listed under “Absolute Maximum Ratings” may cause
permanent damage to the device. This is a stress rating only and functional
operation of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect device reliability.
PIN CONFIGURATION
DIP
CALOK 1
28 MUXIN
CAL 2
27 MUXOUT
–VEE 3
26 REF OUT
+VCC 4
25 REF IN
+VLL 5
24 SPAN/BIP OFF
DGND 6 AD760 23 VOUT
DB7, 15 7
22 AGND
TOP VIEW
DB6, 14 8 (Not to Scale) 21 LDAC
DB5, 13 9
20 CLR
DB4, 12 10
19 SER
DB3, 11 11
18 HBE
DB2, 10, 18/16 SERIAL 12
17 LBE, UNI/BIP CLR
DB1, 9, MSB/LSB 13
16 CS
DB0, 8, SIN 14
15 SOUT
Model
AD760AQ
ORDERING GUIDE
Temperature
Range
Package
Description
–40°C to +85°C Cerdip
Package
Option
Q-28
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection.
Although the AD760 features proprietary ESD protection circuitry, permanent damage may
occur on devices subjected to high energy electrostatic discharges. Therefore, proper ESD
precautions are recommended to avoid performance degradation or loss of functionality.
REV. A
–5–
WARNING!
ESD SENSITIVE DEVICE
5 Page 
AD760
The HC11 generates the requisite 8 clock pulses with data valid
on the rising edges. After the most significant byte is transmit-
ted, the least significant byte (LSBY) is loaded from memory
and transmitted in a similar fashion. To complete the transfer,
the LDAC pin is driven high latching the complete 16-bit word
into the AD760.
INIT
LDAA
STAA
LDAA
STAA
LDAA
STAA
#$2F
PORTD
#$38
DDRD
#$50
SPCR
;SS = 1; SCK = 0; MOSI = I
;SEND TO SPI OUTPUTS
;SS, SCK,MOSI = OUTPUTS
;SEND DATA DIRECTION INFO
;DABL INTRPTS,SPI IS MASTER & ON
;CPOL=0, CPHA=0,1MHZ BAUD RATE
NEXTPT LDAA MSBY ;LOAD ACCUM W/UPPER 8 BITS
BSR SENDAT ;JUMP TO DAC OUTPUT ROUTINE
JMP NEXTPT ;INFINITE LOOP
SENDAT LDY #$1000 ;POINT AT ON-CHIP REGISTERS
BCLR $08,Y,$20 ;DRIVE SS (LDAC) LOW
STAA SPDR ;SEND MS-BYTE TO SPI DATA REG
WAIT1
LDAA
BPL
LDAA
STAA
SPSR
WAIT1
LSBY
SPDR
;CHECK STATUE OF SPIE
;POLL FOR END OF X-MISSION
;GET LOW 8 BITS FROM MEMORY
;SEND LS-BYTE TO SPI DATA REG
WAIT2
LDAA
BPL
BSET
RTS
SPSR ;CHECK STATUS OF SPIE
WAIT2 ;POLL FOR END OF X-MISSION
$08,Y,$20 ;DRIV SS HIGH TO LATCH DATA
the frequency range of interest. The AD760’s noise spectral
density is shown in Figures 13 and 14. Figure 13 shows the
DAC output noise voltage spectral density for a 20 V span ex-
cluding the reference. This figure shows the l/f corner frequency
at 100 Hz and the wideband noise to be below 120 nV/ Hz.
Figure 14 shows the reference wideband noise to be below
125 nV/ Hz.
1000
100
10
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 13. DAC Output Noise Voltage Spectral Density
1000
68HC11
MOSI
SCK
SS
SIN
CS
LDAC
SER
AD760
100
10
Figure 11. AD760 to 68HC11 (SPI) Interface
AD760 TO MICROWIRE INTERFACE
The flexible serial interface of the AD760 is also compatible
with the National Semiconductor MICROWIRE* interface.
The MICROWIRE* interface is used on microcontrollers such
as the COP400 and COP800 series of processors. A generic in-
terface to the MICROWIRE interface is shown in Figure 12.
The G1, SK, and SO pins of the MICROWIRE interface are re-
spectively connected to the LDAC, CS and SIN pins of the
AD760.
MICROWIRE
SO
SK
G1
SIN
CS
LDAC
SER
AD760
Figure 12. AD760 to MICROWIRE Interface
NOISE
In high resolution systems, noise is often the limiting factor. A
16-bit DAC with a 10 volt span has an LSB size of 153 µV
(–96 dB). Therefore, the noise must remain below this level in
*MICROWIRE is a registered trademark of National Semiconductor.
1
1 10 100 1k 10k 100k 1M 10M
FREQUENCY – Hz
Figure 14. Reference Noise Voltage Spectral Density
BOARD LAYOUT
Designing with high resolution data converters requires careful
attention to board layout. Trace impedance is the first issue. A
306 µA current through a 0.5 trace will develop a voltage
drop of 153 µV, which is 1 LSB at the 16-bit level for a 10 V
full-scale span. In addition to ground drops, inductive and ca-
pacitive coupling need to be considered, especially when high
accuracy analog signals share the same board with digital sig-
nals. Finally, power supplies need to be decoupled in order to
filter out ac noise.
Analog and digital signals should not share a common path.
Each signal should have an appropriate analog or digital return
routed close to it. Using this approach, signal loops enclose a
small area, minimizing the inductive coupling of noise. Wide PC
tracks, large gauge wire, and ground planes are highly recom-
mended to provide low impedance signal paths. Separate analog
and digital ground planes should also be used, with a single in-
terconnection point to minimize ground loops. Analog signals
should be routed as far as possible from digital signals and
should cross them at right angles.
REV. A
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD760.PDF ] | |
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