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PDF AD7568 Data sheet ( Hoja de datos )
| Número de pieza | AD7568 | |
| Descripción | LC2MOS Octal 12-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a
LC2MOS
Octal 12-Bit DAC
AD7568
FEATURES
Eight 12-Bit DACs in One Package
4-Quadrant Multiplication
Separate References
Single +5 V Supply
Low Power: 1 mW
Versatile Serial Interface
Simultaneous Update Capability
Reset Function
44-Pin PQFP and PLCC
APPLICATIONS
Process Control
Automatic Test Equipment
General Purpose Instrumentation
GENERAL DESCRIPTION
The AD7568 contains eight 12-bit DACs in one monolithic de-
vice. The DACs are standard current output with separate VREF,
IOUT1, IOUT2 and RFB terminals.
The AD7568 is a serial input device. Data is loaded using
FSIN, CLKIN and SDIN. One address pin, A0, sets up a de-
vice address, and this feature may be used to simplify device
loading in a multi-DAC environment.
All DACs can be simultaneously updated using the asynchro-
nous LDAC input and they can be cleared by asserting the
asynchronous CLR input.
The AD7568 is housed in a space-saving 44-pin plastic quad
flatpack and 44-lead PLCC.
FUNCTIONAL BLOCK DIAGRAM
VDD AGND DGND VREFD VREFC VREF B VREFA R FB A
AD7568
INPUT
LATCH A
12
DAC A
LATCH
12
INPUT
LATCH B
12
DAC B
LATCH
12
INPUT
LATCH C
12
DAC C
LATCH
12
INPUT
LATCH D
12
DAC D
LATCH
12
INPUT
LATCH E
12
DAC E
LATCH
12
INPUT
DAC F
12
LATCH F
LATCH
12
INPUT
DAC G
12
LATCH G
LATCH
12
INPUT
LATCH H
DAC H
12 LATCH
12
DAC A
DAC B
DAC C
DAC D
DAC E
DAC F
DAC G
DAC H
IOUT1A
IOUT2A
RFB B
IOUT1B
IOUT2B
RFB C
IOUT1C
IOUT2C
RFBD
IOUT1D
IOUT2D
RFBE
I OUT1E
IOUT2E
RFBF
IOUT1F
IOUT2F
RFBG
IOUT1G
IOUT2G
RFBH
IOUT1H
IOUT2H
FSIN
CLKIN
SDIN
CONTROL LOGIC
+
INPUT SHIFT
REGISTER 12
A0
SDOUT
LDAC CLR VREF E VREF F VREF G VREF H
PIN CONFIGURATIONS
Plastic Quad Flatpack
Plastic Leaded Chip Carrier
NC 1
VREF F 2
R FB F 3
IOUT1F 4
IOUT2F 5
VREF G 6
R FB G 7
IOUT1G 8
IOUT2G 9
VREF H 10
R FB H 11
PIN 1 IDENTIFIER
AD7568 PQFP
TAODP 7VI5E6W8
NoTtOtoP SVcIEaWle
(Not to Scale)
33 NC
32 VREFC
31 RFB C
30 IOUT1C
29 IOUT2C
28 VREFB
27 RFB B
26 IOUT1B
25 IOUT2B
24 VREFA
23 R FB A
6 5 4 3 2 1 44 43 42 41 40
NC 7
VREF F 8
RFB F 9
IOUT1 F 10
IOUT2 F 11
VREF G 12
RFB G 13
IOUT1 G 14
IOUT2 G 15
VREF H 16
RFB H 17
AD7568 PLCC
TOP VIEW
(Not to Scale)
39 NC
38 VREF C
37 RFB C
36 IOUT1 C
35 IOUT2 C
34 VREF B
33 RFB B
32 IOUT1 B
31 IOUT2 B
30 VREF A
29 RFB A
18 19 20 21 22 23 24 25 26 27 28
REV. B
NC = NO CONNECT
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
NC = NO CONNECT
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD7568
TERMINOLOGY
Relative Accuracy
Relative Accuracy or endpoint linearity is a measure of the
maximum deviation from a straight line passing through the
endpoints of the DAC transfer function. It is measured after
adjusting for zero error and full-scale error and is normally ex-
pressed in Least Significant Bits or as a percentage or full-scale
reading.
Differential Nonlinearity
Differential nonlinearity is the difference between the measured
change and the ideal 1 LSB change between any two adjacent
codes. A specified differential nonlinearity of 1 LSB maximum
ensures monotonicity.
Gain Error
Gain Error is a measure of the output error between an ideal
DAC and the actual device output. It is measured with all 1s in
the DAC after offset error has been adjusted out and is
expressed in Least Significant Bits. Gain error is adjustable to
zero with an external potentiometer.
Output Leakage Current
Output leakage current is current which flows in the DAC lad-
der switches when these are turned off. For the IOUT1 terminal,
it can be measured by loading all 0s to the DAC and measuring
the IOUT1 current. Minimum current will flow in the IOUT2 line
when the DAC is loaded with all 1s. This is a combination of
the switch leakage current and the ladder termination resistor
current. The IOUT2 leakage current is typically equal to that in
IOUT1.
Output Capacitance
This is the capacitance from the IOUT1 pin to AGND.
Output Voltage Settling Time
This is the amount of time it takes for the output to settle to a
specified level for a full-scale input change. For the AD7568, it
is specified with the AD843 as the output op amp.
Digital to Analog Glitch Impulse
This is the amount of charge injected into the analog output
when the inputs change state. It is normally specified as the area
of the glitch in either pA-secs or nV-secs, depending upon
whether the glitch is measured as a current or voltage signal. It
is measured with the reference input connected to AGND and
the digital inputs toggled between all 1s and all 0s.
AC Feedthrough Error
This is the error due to capacitive feedthrough from the DAC
reference input to the DAC IOUT terminal, when all 0s are
loaded in the DAC.
Channel-to-Channel Isolation
Channel-to-channel isolation refers to the proportion of input
signal from one DAC’s reference input which appears at the
output of any other DAC in the device and is expressed in dBs.
Digital Crosstalk
The glitch impulse transferred to the output of one converter
due to a change in digital input code to the other converter is
defined as the Digital Crosstalk and is specified in nV-secs.
Digital Feedthrough
When the device is not selected, high frequency logic activity on
the device digital inputs is capacitively coupled through the de-
vice to show up as noise on the IOUT pin and subsequently on
the op amp output. This noise is digital feedthrough.
Table I. AD7568 Loading Sequence
DB15
DB0
DB11 DB10 DB9 DB8 DB7 DB6 DB5 DB4 DB3 DB2 DB1 DB0 A0 DS2 DS1 DS0
Table II. DAC Selection
DS2 DS1 DS0 Function
0 0 0 DAC A Selected
0 0 1 DAC B Selected
0 1 0 DAC C Selected
0 1 1 DAC D Selected
1 0 0 DAC E Sclected
1 0 1 DAC F Selected
1 1 0 DAC G Sclected
1 1 1 DAC H Selected
REV. B
–5–
5 Page 
AD7568
68HC11*
PC5
PC6
PC7
SCK
MOSI
AD7568*
CLR
LDAC
FSIN
CLKIN
SDIN
TMS320C25*
XF
FSX
DX
CLKX
AD7568*
+5V
CLR
LDAC
FSIN
SDIN
CLKIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 21. AD7568 to 68HC11 Interface
In Figure 21, LDAC and CLR are controlled by the PC6 and
PC5 port outputs. As with the 80C51, each DAC of the
AD7568 can be updated after each two-byte transfer, or else all
DACs can be simultaneously updated.
AD7568–ADSP-2101 Interface
Figure 22 shows a serial interface between the AD7568 and the
ADSP-2101 digital signal processor. The ADSP-2101 may be
set up to operate in the SPORT Transmit Normal Internal
Framing Mode. The following ADSP-2101 conditions are rec-
ommended: Internal SCLK; Active High Framing Signal; 16-bit
word length. Transmission is initiated by writing a word to the
TX register after the SPORT has been enabled. The data is then
clocked out on every rising edge of SCLK after TFS goes low.
TFS stays low until the next data transfer.
ADSP-2101*
FO
TFS
DT
SCLK
AD7568*
+5V
CLR
LDAC
FSIN
SDIN
CLKIN
CLOCK
GENERATION
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 23. AD7568 to TMS320C25 Interface
with the MSB, is then shifted out to the DX pin on the rising
edge of CLKX. When all bits have been transmitted, the user
can update the DAC outputs by bringing the XF output flag low.
Multiple DAC Systems
If there are only two AD7568s in a system, there is a simple way
of programming each. This is shown in Figure 24. If the user
wishes to program one of the DACs in the first AD7568, then
DB3 of the serial bit stream should be set to 0, to correspond to
the state of the A0 pin on that device. If the user wishes to pro-
gram a DAC in the second AD7568, then DB3 should be set to
1, to correspond to A0 on that device.
ADSP-2101*
FO
TFS
DT
SCLK
AD7568*
A0
+5V CLR
LDAC
FSIN
SDIN
CLKIN
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 22. AD7568 to ADSP-2101 Interface
AD7568–TMS320C25 Interface
Figure 23 shows an interface circuit for the TMS320C25
digital signal processor. The data on the DX pin is clocked
out of the processor’s Transmit Shift Register by the CLKX
signal. Sixteen-bit transmit format should be chosen by setting
the FO bit in the ST1 register to 0. The transmit operation be-
gins when data is written into the data transmit register of the
TMS320C25. This data will be transmitted when the FSX line
goes low while CLKX is high or going high. The data, starting
AD7568*
LDAC
FSIN
SDIN
CLKIN
A0
+5V CLR
*ADDITIONAL PINS OMITTED FOR CLARITY
Figure 24. Interfacing ADSP-2101 to Two AD7568s
REV. B
–11–
11 Page | ||
| Páginas | Total 12 Páginas | |
| PDF Descargar | [ Datasheet AD7568.PDF ] | |
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