PDF AD7541A Data sheet ( Hoja de datos )

Número de pieza	AD7541A
Descripción	CMOS 12-Bit Monolithic Multiplying DAC
Fabricantes	Analog Devices
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No Preview Available ! a CMOS 12-Bit Monolithic Multiplying DAC AD7541A FEATURES Improved Version of AD7541 Full Four-Quadrant Multiplication 12-Bit Linearity (Endpoint) All Parts Guaranteed Monotonic TTL/CMOS Compatible Low Cost Protection Schottky Diodes Not Required Low Logic Input Leakage GENERAL DESCRIPTION The Analog Devices AD7541A is a low cost, high performance 12-bit monolithic multiplying digital-to-analog converter. It is fabricated using advanced, low noise, thin film on CMOS technology and is available in a standard 18-lead DIP and in 20-terminal surface mount packages. The AD7541A is functionally and pin compatible with the in- dustry standard AD7541 device and offers improved specifica- tions and performance. The improved design ensures that the device is latch-up free so no output protection Schottky diodes are required. This new device uses laser wafer trimming to provide full 12-bit endpoint linearity with several new high performance grades. ORDERING GUIDE1 Model2 Temperature Range AD7541AJN 0°C to +70°C AD7541AKN 0°C to +70°C AD7541AJP 0°C to +70°C AD7541AKP 0°C to +70°C AD7541AKR 0°C to +70°C AD7541AAQ –25°C to +85°C AD7541ABQ –25°C to +85°C AD7541ASQ –55°C to +125°C AD7541ATQ –55°C to +125°C AD7541ASE –55°C to +125°C AD7541ATE –55°C to +125°C Relative Gain Accuracy Error TMIN to TMAX TA = +25؇C ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 1 LSB ± 1/2 LSB ± 6 LSB ± 1 LSB ±6 ±1 ±1 ± 6 LSB ± 1 LSB ± 6 LSB ± 1 LSB ± 1 LSB ± 1/2 LSB ± 6 LSB ± 1 LSB Package Options3 N-18 N-18 P-20A P-20A R-18 Q-18 Q-18 Q-18 Q-18 E-20A E-20A NOTES 1Analog Devices reserves the right to ship either ceramic (D-18) or cerdip (Q-18) hermetic packages. 2To order MIL-STD-883, Class B process parts, add /883B to part number. Contact local sales office for military data sheet. 3E = Leadless Ceramic Chip Carrier; N = Plastic DIP; P = Plastic Leaded Chip Carrier; Q = Cerdip; R = Small Outline IC. VREF FUNCTIONAL BLOCK DIAGRAM 10kΩ 10kΩ 10kΩ 20kΩ S1 20kΩ S2 20kΩ S3 20kΩ S12 20kΩ 10kΩ BIT 1 (MSB) BIT 2 BIT 3 BIT 12 (LSB) DIGITAL INPUTS (DTL/TTL/CMOS COMPATIBLE) LOGIC: A SWITCH IS CLOSED TO IOUT1 FOR ITS DIGITAL INPUT IN A "HIGH" STATE. OUT2 OUT1 RFEEDBACK PRODUCT HIGHLIGHTS Compatibility: The AD7541A can be used as a direct replace- ment for any AD7541-type device. As with the Analog Devices AD7541, the digital inputs are TTL/CMOS compatible and have been designed to have a ± 1 µA maximum input current requirement so as not to load the driving circuitry. Improvements: The AD7541A offers the following improved specifications over the AD7541: 1. Gain Error for all grades has been reduced with premium grade versions having a maximum gain error of ± 3 LSB. 2. Gain Error temperature coefficient has been reduced to 2 ppm/°C typical and 5 ppm/°C maximum. 3. Digital-to-analog charge injection energy for this new device is typically 20% less than the standard AD7541 part. 4. Latch-up proof. 5. Improvements in laser wafer trimming provides 1/2 LSB max differential nonlinearity for top grade devices over the operat- ing temperature range (vs. 1 LSB on older 7541 types). 6. All grades are guaranteed monotonic to 12 bits over the operating temperature range. REV. B Information furnished by Analog Devices is believed to be accurate and reliable. However, no responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Analog Devices. One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A. Tel: 617/329-4700 World Wide Web Site: http://www.analog.com Fax: 617/326-8703 © Analog Devices, Inc., 1997 1 page AD7541A BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION) Figure 5 and Table III illustrate the circuitry and code relation- ship for bipolar operation. With a dc reference (positive or nega- tive polarity) the circuit provides offset binary operation. With an ac reference the circuit provides full 4-quadrant multiplication. With the DAC loaded to 1000 0000 0000, adjust R1 for VOUT = 0 V (alternatively, one can omit R1 and R2 and adjust the ratio of R3 to R4 for VOUT = 0 V). Full-scale trimming can be accomplished by adjusting the amplitude of VREF or by vary- ing the value of R5. As in unipolar operation, A1 must be chosen for low VOS and low IB. R3, R4 and R5 must be selected for matching and track- ing. Mismatch of 2R3 to R4 causes both offset and full-scale error. Mismatch of R5 to R4 or 2R3 causes full-scale error. C1 phase compensation (10 pF to 50 pF) may be required for sta- bility, depending on amplifier used. VDD 16 18 R2* C1 33pF R4 20kΩ VDD RFB OUT1 1 VIN R1* 17 VREF AD7541A OUT2 2 PINS 4–15 GND 3 A1 AD544L R3 10kΩ R6 5kΩ 10% R5 20kΩ A2 AD544J VOUT BIT 1 – BIT 12 DIGITAL GROUND ANALOG COMMON FOR VALUES OF R1 AND R2 SEE TABLE 1. Figure 5. Bipolar Operation (4-Quadrant Multiplication) Table III. Bipolar Code Table for Offset Binary Circuit of Figure 5 Binary Number in DAC MSB LSB Analog Output, VOUT 1111 1111 1111 1000 0000 1000 0000 0001 0000 0111 1111 1111 0000 0000 0000  2047  +VIN  2048   1 +VIN  2048  0 Volts  1 –VIN  2048   2048  –VIN  2048  Figure 6 and Table IV show an alternative method of achieving bipolar output. The circuit operates with sign plus magnitude code and has the advantage of giving 12-bit resolution in each quadrant, compared with 11-bit resolution per quadrant for the circuit of Figure 5. The AD7592 is a fully protected CMOS changeover switch with data latches. R4 and R5 should match each other to 0.01% to maintain the accuracy of the D/A con- verter. Mismatch between R4 and R5 introduces a gain error. VDD R2 16 18 C1 33pF VDD RFB OUT1 1 VIN R1* 17 VREF AD7541A OUT2 2 PINS 4–15 GND 3 A1 AD544L SIGN BIT DIGITAL GROUND ANALOG COMMON R4 20kΩ R5 20kΩ R3 10kΩ 10% VOUT A2 AD544J 1/2 AD7592JN BIT 1 – BIT 12 *FOR VALUES OF R1 AND R2 SEE TABLE 1. Figure 6. 12-Bit Plus Sign Magnitude Operation Table IV. 12-Bit Plus Sign Magnitude Code Table for Circuit of Figure 6 Sign Binary Number in DAC Bit MSB LSB Analog Output, VOUT 0 1111 1111 1111 0 0000 0000 0000 1 0000 0000 0000 1 1111 1111 1111 Note: Sign bit of “0” connects R3 to GND.  4095  +VIN ×  4096  0 Volts 0 Volts  4095  –VIN ×  4096  REV. B –5– 5 Page

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