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Número de pieza | AD7541 | |
Descripción | 12-Bit/ Multiplying D/A Converter | |
Fabricantes | Intersil Corporation | |
Logotipo | ||
Hay una vista previa y un enlace de descarga de AD7541 (archivo pdf) en la parte inferior de esta página. Total 8 Páginas | ||
No Preview Available ! AD7541
August 1997
12-Bit, Multiplying D/A Converter
Features
• 12-Bit Linearity 0.01%
• Pretrimmed Gain
• Low Gain and Linearity Tempcos
• Full Temperature Range Operation
• Full Input Static Protection
• TTL/CMOS Compatible
• +5V to +15V Supply Range
• 20mW Low Power Dissipation
• Current Settling Time 1µs to 0.01% of FSR
• Four Quadrant Multiplication
Description
The AD7541 is a monolithic, low cost, high performance,
12-bit accurate, multiplying digital-to-analog converter
(DAC).
Intersil’ wafer level laser-trimmed thin-film resistors on
CMOS circuitry provide true 12-bit linearity with TTL/CMOS
compatible operation.
Special tabbed-resistor geometries (improving time stability),
full input protection from damage due to static discharge by
diode clamps to V+ and ground, large IOUT1 and IOUT2 bus
lines (improving superposition errors) are some of the fea-
tures offered by Intersil AD7541.
Pin compatible with AD7521, this DAC provides accurate
four quadrant multiplication over the full military temperature
range.
Ordering Information
PART NUMBER
NONLINEARITY
TEMP. RANGE (oC)
PACKAGE
PKG. NO.
AD7541JN
0.02% (11-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541KN
0.01% (12-Bit)
0 to 70
18 Ld PDIP
E18.3
AD7541LN
0.01% (12-Bit) Guaranteed
Monotonic
0 to 70
18 Ld PDIP
E18.3
Pinout
AD7541
(PDIP)
TOP VIEW
IOUT1 1
IOUT2 2
GND 3
BIT 1 (MSB) 4
BIT 2 5
BIT 3 6
BIT 4 7
BIT 5 8
BIT 6 9
18 RFEEDBACK
17 VREF IN
16 V+
15 BIT 12 (LSB)
14 BIT 11
13 BIT 10
12 BIT 9
11 BIT 8
10 BIT 7
Functional Block Diagram
VREF IN
(17)
20kΩ
10kΩ 10kΩ
20kΩ 20kΩ
10kΩ
10kΩ
20kΩ
20kΩ
20kΩ
(3)
SPDT
NMOS
SWITCHES
MSB
(4)
BIT 2
(5)
BIT 3
(6)
IOUT2 (2)
IOUT1 (1)
10kΩ
RFEEDBACK
(18)
NOTE: Switches shown for digital inputs “High”.
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures.
http://www.intersil.com or 407-727-9207 | Copyright © Intersil Corporation 1999
10-9
File Number 3107.1
1 page AD7541
A “Logic 1” input at any digital input forces the corresponding
ladder switch to steer the bit current to IOUT1 bus. A “Logic
0” input forces the bit current to IOUT2 bus. For any code the
IOUT1 and IOUT2 bus currents are complements of one
another. The current amplifier at IOUT2 changes the polarity
of IOUT2 current and the transconductance amplifier at
IOUT1 output sums the two currents. This configuration dou-
bles the output range of the DAC. The difference current
resulting at zero offset binary code, (MSB = “Logic 1”, All
other bits = “Logic 0”), is corrected by using an external
resistive divider, from VREF to IOUT2.
Offset Adjustment
Gain Adjustment
1. Connect all digital inputs to VDD.
2. Monitor VOUT for a -VREF (1 - 1/211) volts reading.
3. To increase VOUT, connect a series resistor, (0Ω to
250Ω), in the IOUT1 amplifier feedback loop.
4. To decrease VOUT, connect a series resistor, (0Ω to 250Ω),
between the reference voltage and the VREF terminal.
TABLE 2. CODE TABLE - BIPOLAR (OFFSET BINARY)
OPERATION
1. Adjust VREF to approximately +10V.
2. Set R4 to zero.
3. Connect all digital inputs to “Logic 1”.
4. Adjust IOUT1 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT2 amplifier output.
5. Connect a short circuit across R2.
6. Connect all digital inputs to “Logic 0”.
7. Adjust IOUT2 amplifier offset zero adjust trimpot for 0V
±0.1mV at IOUT1 amplifier output.
8. Remove short circuit across R2.
DIGITAL INPUT
111111111111
100000000001
100000000000
011111111111
000000000001
000000000000
ANALOG OUTPUT
-VREF (1 - 1/211)
-VREF (1/211)
0
VREF (1/211)
VREF (1 - 1/211)
VREF
9. Connect MSB (Bit 1) to “Logic 1” and all other bits to “Logic 0”.
10. Adjust R4 for 0V ±0.2mV at VOUT.
±10V
VREF
+15V
BIT 1 (MSB) 17
4
16
18
1
IOUT1
DIGITAL
INPUT
AD7541
15
BIT 12 (LSB)
2
3 IOUT2
GND
-
6 A1
+
R1 10K
R2 10K
R5 10K
-
6 A2
+
VOUT
R3
390K
R4
500Ω
NOTE: R1 and R2 should be 0.01%, low-TCR resistors.
FIGURE 3. BIPOLAR OPERATION (4-QUADRANT MULTIPLICATION)
10-13
5 Page |
Páginas | Total 8 Páginas | |
PDF Descargar | [ Datasheet AD7541.PDF ] |
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