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PDF AD9709 Data sheet ( Hoja de datos )
| Número de pieza | AD9709 | |
| Descripción | Dual TxDAC+ Digital-to-Analog Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9709 (archivo pdf) en la parte inferior de esta página. Total 30 Páginas | ||
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FEATURES
8-bit dual transmit digital-to-analog converter (DAC)
125 MSPS update rate
Excellent SFDR to Nyquist @ 5 MHz output: 66 dBc
Excellent gain and offset matching: 0.1%
Fully independent or single-resistor gain control
Dual port or interleaved data
On-chip 1.2 V reference
Single 5 V or 3.3 V supply operation
Power dissipation: 380 mW @ 5 V
Power-down mode: 50 mW @ 5 V
48-lead LQFP
APPLICATIONS
Communications
Base stations
Digital synthesis
Quadrature modulation
3D ultrasound
GENERAL DESCRIPTION
The AD97091 is a dual-port, high speed, 2-channel, 8-bit CMOS
DAC. It integrates two high quality 8-bit TxDAC+® cores, a voltage
reference, and digital interface circuitry into a small 48-lead LQFP
package. The AD9709 offers exceptional ac and dc performance
while supporting update rates of up to 125 MSPS.
The AD9709 has been optimized for processing I and Q data in
communications applications. The digital interface consists of two
double-buffered latches as well as control logic. Separate write
inputs allow data to be written to the two DAC ports independent
of one another. Separate clocks control the update rate of the DACs.
A mode control pin allows the AD9709 to interface to two separate
data ports, or to a single interleaved high speed data port. In inter-
leaving mode, the input data stream is demuxed into its original
I and Q data and then latched. The I and Q data is then converted
by the two DACs and updated at half the input data rate.
The GAINCTRL pin allows two modes for setting the full-scale
current (IOUTFS) of the two DACs. IOUTFS for each DAC can be set
independently using two external resistors, or IOUTFS for both
DACs can be set by using a single external resistor. See the Gain
Control Mode section for important date code information on
this feature.
The DACs utilize a segmented current source architecture
combined with a proprietary switching technique to reduce
1 Patent pending.
Rev. B
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
8-Bit, 125 MSPS, Dual TxDAC+
Digital-to-Analog Converter
AD9709
FUNCTIONAL BLOCK DIAGRAM
DVDD1/ DCOM1/
DVDD2 DCOM2 AVDD ACOM CLK1
PORT1
WRT1/IQWRT
WRT2/IQSEL
PORT2
1
LATCH
1
DAC
DIGITAL
INTERFACE
AD9709
REFERENCE
BIAS
GENERATOR
2
LATCH
2
DAC
MODE
CLK2/IQ RESET
Figure 1.
IOUTA1
IOUTB1
REFIO
FSADJ1
FSADJ2
GAINCTRL
SLEEP
IOUTA2
IOUTB2
glitch energy and to maximize dynamic accuracy. Each DAC
provides differential current output, thus supporting single-
ended or differential applications. Both DACs can be
simultaneously updated and provide a nominal full-scale
current of 20 mA. The full-scale currents between each DAC
are matched to within 0.1%.
The AD9709 is manufactured on an advanced low-cost CMOS
process. It operates from a single supply of 3.3 V or 5 V and
consumes 380 mW of power.
PRODUCT HIGHLIGHTS
1. The AD9709 is a member of a pin-compatible family of
dual TxDACs providing 8-, 10-, 12-, and 14-bit resolution.
2. Dual 8-Bit, 125 MSPS DACs. A pair of high performance
DACs optimized for low distortion performance provide
for flexible transmission of I and Q information.
3. Matching. Gain matching is typically 0.1% of full scale, and
offset error is better than 0.02%.
4. Low Power. Complete CMOS dual DAC function operates
at 380 mW from a 3.3 V or 5 V single supply. The DAC
full-scale current can be reduced for lower power operation,
and a sleep mode is provided for low power idle periods.
5. On-Chip Voltage Reference. The AD9709 includes a 1.20 V
temperature-compensated band gap voltage reference.
6. Dual 8-Bit Inputs. The AD9709 features a flexible dual-
port interface, allowing dual or interleaved input data.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2009 Analog Devices, Inc. All rights reserved.
1 page  
AD9709
DYNAMIC SPECIFICATIONS
TMIN to TMAX, AVDD = 3.3 V or 5 V, DVDD1 = DVDD2 = 3.3 V or 5 V, IOUTFS = 20 mA, differential transformer-coupled output, 50 Ω
doubly terminated, unless otherwise noted.
Table 2.
Parameter
DYNAMIC PERFORMANCE
Maximum Output Update Rate (fCLK)
Output Settling Time (tST) to 0.1%1
Output Propagation Delay (tPD)
Glitch Impulse
Output Rise Time (10% to 90%)1
Output Fall Time (90% to 10%)1
Output Noise (IOUTFS = 20 mA)
Output Noise (IOUTFS = 2 mA)
AC LINEARITY
Spurious-Free Dynamic Range to Nyquist
fCLK = 100 MSPS, fOUT = 1.00 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
fCLK = 65 MSPS, fOUT = 1.00 MHz
fCLK = 65 MSPS, fOUT = 2.51 MHz
fCLK = 65 MSPS, fOUT = 5.02 MHz
fCLK = 65 MSPS, fOUT = 14.02 MHz
fCLK = 65 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 25 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Signal to Noise and Distortion Ratio
fCLK = 50 MHz, fOUT = 1 MHz
Total Harmonic Distortion
fCLK = 100 MSPS, fOUT = 1.00 MHz
fCLK = 50 MSPS, fOUT = 2.00 MHz
fCLK = 125 MSPS, fOUT = 4.00 MHz
fCLK = 125 MSPS, fOUT = 10.00 MHz
Multitone Power Ratio (Eight Tones at 110 kHz Spacing)
fCLK = 65 MSPS, fOUT = 2.00 MHz to 2.99 MHz
0 dBFS Output
–6 dBFS Output
–12 dBFS Output
–18 dBFS Output
Channel Isolation
fCLK = 125 MSPS, fOUT = 10 MHz
fCLK = 125 MSPS, fOUT = 40 MHz
Min Typ Max Unit
125
35
1
5
2.5
2.5
50
30
MSPS
ns
ns
pV-s
ns
ns
pA/√Hz
pA/√Hz
63 68
62
56
50
68
68
66
60
50
63
55
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
dBc
50 dB
−67 −63
−63
−63
−63
dBc
dBc
dBc
dBc
58 dBc
51 dBc
46 dBc
41 dBc
85 dBc
77 dBc
1 Measured single-ended into 50 Ω load.
Rev. B | Page 4 of 32
5 Page 
AD9709
75
70
fOUT = 10MHz
65
fOUT = 25MHz
60
fOUT = 40MHz
55
fOUT = 60MHz
50
45
–50 –30 –10
10
30
50
70
90
TEMPERATURE (°C)
Figure 16. SFDR vs. Temperature @ fCLK = 125 MSPS, 0 dBFS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
10 20 30 40 50
FREQUENCY (MHz)
Figure 19. Dual-Tone SFDR @ fCLK = 125 MSPS
60
0.05 1.0
0.03
OFFSET ERROR
0
GAIN ERROR
0.5
0
–0.03
–0.5
–0.05
–40
–20
0 20 40
TEMPERATURE (°C)
60
–1.0
80
Figure 17. Gain and Offset Error vs. Temperature @ fCLK = 125 MSPS
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
0
10 20 30 40 50
FREQUENCY (MHz)
Figure 20. Four-Tone SFDR @ fCLK = 125 MSPS
60
0
–10
–20
–30
–40
–50
–60
–70
–80
–90
–100
0
10 20 30 40 50
FREQUENCY (MHz)
Figure 18. Single-Tone SFDR @ fCLK = 125 MSPS
60
Rev. B | Page 10 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD9709.PDF ] | |
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