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PDF AD9410 Data sheet ( Hoja de datos )
| Número de pieza | AD9410 | |
| Descripción | 210 MSPS ADC | |
| Fabricantes | Analog Devices | |
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FEATURES
SNR = 54 dB with 99 MHz analog input
500 MHz analog bandwidth
On-chip reference and track and hold
1.5 V p-p differential analog input range
5.0 V and 3.3 V supply operation
3.3 V CMOS/TTL outputs
Power: 2.1 W typical at 210 MSPS
Demultiplexed outputs each at 105 MSPS
Output data format option
Data sync input and data clock output provided
Interleaved or parallel data output option
APPLICATIONS
Communications and radars
Local multipoint distribution services (LMDS)
High-end imaging systems and projectors
Cable reverse paths
Point-to-point radio links
GENERAL DESCRIPTION
The AD9410 is a 10-bit monolithic sampling analog-to-digital
converter (ADC) with an on-chip track-and-hold circuit and is
optimized for high speed conversion and ease of use. The product
operates at a 210 MSPS conversion rate, with outstanding
dynamic performance over its full operating range.
The ADC requires a 5.0 V and 3.3 V power supply and up to a
210 MHz differential clock input for full performance operation.
No external reference or driver components are required for many
applications. The digital outputs are TTL-/CMOS-compatible and
separate output power supply pins also support interfacing with
3.3 V logic.
The clock input is differential and TTL-/CMOS-compatible.
The 10-bit digital outputs can be operated from 3.3 V (2.5 V to
3.6 V) supplies. Two output buses support demultiplexed data
up to 105 MSPS rates and binary or twos complement output
coding format is available. A data sync function is provided for
timing-dependent applications. An output clock simplifies
interfacing to external logic. The output data bus timing is
selectable for parallel or interleaved mode, allowing for
flexibility in latching output data.
10-Bit,
210 MSPS ADC
AD9410
AIN
AIN
DS
DS
CLK+
CLK–
FUNCTIONAL BLOCK DIAGRAM
REFIN REFOUT AGND DGND VD VDD VCC
REFERENCE
ADC
T/H 10-BIT
CORE
TIMING AND
SYNCHRONIZATION
AD9410
PORT 10
A
10
PORT 10
B
DFS
I/P
Figure 1.
ORA
DA9–DA0
ORB
DB9–DB0
DCO
DCO
Fabricated on an advanced BiCMOS process, the AD9410 is
available in an 80-lead thin quad flat package, exposed pad
specified over the industrial temperature range (−40°C to +85°C).
PRODUCT HIGHLIGHTS
1. High Resolution at High Speed—The architecture is spe-
cifically designed to support conversion up to 210 MSPS
with outstanding dynamic performance.
2. Demultiplexed Output—Output data is decimated by two
and provided on two data ports for ease of data transport.
3. Output Data Clock—The AD9410 provides an output data
clock synchronous with the output data, simplifying the
timing between data and other logic.
4. Data Synchronization—A DS input is provided to allow for
synchronization of two or more AD9410s in a system, or to
synchronize data to a specific output port in a single
AD9410 system.
Rev. A
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113 ©2000–2007 Analog Devices, Inc. All rights reserved.
1 page  
AD9410
SWITCHING SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 2.
Parameter
SWITCHING PERFORMANCE
Maximum Conversion Rate
Minimum Conversion Rate
Clock Pulse Width High, tEH
Clock Pulse Width Low, tEL
Aperture Delay, tA
Aperture Uncertainty (Jitter)
Output Valid Time, tV
Output Propagation Delay, tPD
Output Rise Time, tR
Output Fall Time, tF
CLKOUT Propagation Delay, tCPD1
Data to DCO Skew, (tPD – tCPD)
DS Setup Time, tSDS
DS Hold Time, tHDS
Interleaved Mode (A, B Latency)
Parallel Mode (A, B Latency)
Temp
Full
Full
25°C
25°C
25°C
25°C
Full
Full
25°C
25°C
Full
Full
Full
Full
Full
Full
Test Level
VI
IV
IV
IV
V
V
VI
VI
V
V
VI
IV
IV
IV
VI
VI
Min Typ
210
1.2 2.4
1.2 2.4
1.0
0.65
3.0
1.8
1.4
2.6 4.8
01
0.5
0
A = 6, B = 6
A = 7, B = 6
Max Unit
MSPS
100 MSPS
ns
ns
ns
ps rms
ns
7.4 ns
ns
ns
6.4 ns
2 ns
ns
ns
Cycles
Cycles
1 CLOAD = 5 pF.
DIGITAL SPECIFICATIONS
VDD = 3.3 V, VD = 3.3 V, VCC = 5.0 V; 2.5 V external reference; AIN = −0.5 dBFS; clock input = 210 MSPS; TA = 25°C; unless otherwise noted.
Table 3.
Parameter
DIGITAL INPUTS
DFS, Input Logic 1 Voltage
DFS, Input Logic 0 Voltage
DFS, Input Logic 1 Current
DFS, Input Logic 0 Current
I/P Input Logic 1 Current1
I/P Input Logic 0 Current1
CLK+, CLK− Differential Input Voltage
CLK+, CLK− Differential Input Resistance
CLK+, CLK− Common-Mode Input Voltage2
DS, DS Differential Input Voltage
DS, DS Common-Mode Input Voltage
Digital Input Pin Capacitance
DIGITAL OUTPUTS
Logic 1 Voltage (VDD = 3.3 V)
Logic 0 Voltage (VDD = 3.3 V)
Output Coding
Temp Test Level Min
Full IV
Full IV
Full V
Full V
Full V
Full V
Full IV
Full V
Full V
Full IV
Full V
25°C V
4
0.4
0.4
Typ Max
1
50
50
400
1
1.6
1.5
1.5
3
Full VI
Full VI
VDD – 0.05
0.05
Binary or Twos Complement
Unit
V
V
μA
μA
μA
μA
V
kΩ
V
V
V
pF
V
V
1 I/P pin Logic 1 = 5 V, Logic 0 = GND. It is recommended to use a series 2.5 kΩ (±10%) resistor to VDD when setting to Logic 1 to limit input current.
2 See Clock Input section.
Rev. A | Page 4 of 20
5 Page 
AD9410
TERMINOLOGY
Analog Bandwidth
The analog input frequency at which the spectral power of the
fundamental frequency (as determined by the FFT analysis) is
reduced by 3 dB.
Aperture Delay
The delay between the 50% point of the rising edge of the clock
command and the instant at which the analog input is sampled.
Aperture Uncertainty (Jitter)
The sample-to-sample variation in aperture delay.
Differential Analog Input Resistance, Differential Analog
Input Capacitance, and Differential Analog Input Impedance
The real and complex impedances measured at each analog
input port. The resistance is measured statically and the
capacitance and differential input impedances are measured
with a network analyzer.
Differential Analog Input Voltage Range
The peak-to-peak differential voltage that must be applied to
the converter to generate a full-scale response. Peak differential
voltage is computed by observing the voltage on a single pin
and subtracting the voltage from the other pin, which is 180°
out of phase. Peak-to-peak differential is computed by rotating
the inputs phase 180° and taking the peak measurement again.
The difference is then computed between both peak
measurements.
Differential Nonlinearity
The deviation of any code width from an ideal 1 LSB step.
Effective Number of Bits (ENOB)
ENOB is calculated from the measured SINAD based on the
equation
ENOB =
SINAD
MEASURED
− 1.76
dB
+
20
log⎜⎜⎝⎛
Full Scale Amplitude
Input Amplitude
⎟⎞
⎟⎠
6.02
Clock Pulse Width/Duty Cycle
Pulse width high is the minimum amount of time that the clock
pulse should be left in Logic 1 state to achieve rated performance;
pulse width low is the minimum time the clock pulse should be
left in low state. At a given clock rate, these specifications define
an acceptable clock duty cycle.
Full-Scale Input Power
Expressed in dBm. Computed using the equation
⎡⎤
POWERFULLSCALE
= 10 log⎢⎢V 2 FULLSCALErms
⎢
⎢⎣
Z INPUT
0.001
⎥
⎥
⎥
⎥⎦
Harmonic Distortion, Second
The ratio of the rms signal amplitude to the rms value of the
second harmonic component, reported in dBc.
Harmonic Distortion, Third
The ratio of the rms signal amplitude to the rms value of the
third harmonic component, reported in dBc.
Integral Nonlinearity
The deviation of the transfer function from a reference line
measured in fractions of 1 LSB using a best straight line
determined by a least-square curve fit.
Minimum Conversion Rate
The clock rate at which the SNR of the lowest analog
signal frequency drops by no more than 3 dB below the
guaranteed limit.
Maximum Conversion Rate
The clock rate at which parametric testing is performed.
Output Propagation Delay
The delay between a differential crossing of CLK+ and
CLK− and the time when all output data bits are within valid
logic levels.
Out-of-Range Recovery Time
Out-of-range recovery time is the time it takes for the ADC to
reacquire the analog input after a transient from 10% above
positive full scale to 10% above negative full scale, or from 10%
below negative full scale to 10% below positive full scale.
Noise (For Any Range Within the ADC)
VNOISE =
| Z |× 0.001 × 10⎜⎛ FSdBm − SIGNALdBFS ⎟⎞
⎝ 10 ⎠
where:
Z is the input impedance.
FS is the full scale of the device for the frequency in question.
SIGNAL is the signal level within the ADC reported in dB
below full scale. This value includes both thermal and
quantization noise.
Power Supply Rejection Ratio (PSRR)
The ratio of a change in input offset voltage to a change in
power supply voltage.
Rev. A | Page 10 of 20
11 Page | ||
| Páginas | Total 21 Páginas | |
| PDF Descargar | [ Datasheet AD9410.PDF ] | |
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