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PDF AD9054 Data sheet ( Hoja de datos )
| Número de pieza | AD9054 | |
| Descripción | 8-Bit/ 200 MSPS A/D Converter | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD9054 (archivo pdf) en la parte inferior de esta página. Total 20 Páginas | ||
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a
8-Bit, 200 MSPS
A/D Converter
AD9054
FEATURES
200 MSPS Guaranteed Conversion Rate
135 MSPS Low Cost Version Available
350 MHz Analog Bandwidth
1 V p-p Analog Input Range
Internal +2.5 V Reference and T/H
Low Power: 500 mW
+5 V Single Supply Operation
TTL Output Interface
Single or Demultiplexed Output Ports
APPLICATIONS
RGB Graphics Processing
High Resolution Video
Digital Data Storage Read Channels
Digital Communications
Digital Instrumentation
Medical Imaging
GENERAL DESCRIPTION
The AD9054 is an 8-bit monolithic analog-to-digital converter
optimized for high speed, low power, small size and ease of use.
With a 200 MSPS encode rate capability and full-power analog
bandwidth of 350 MHz, the component is ideal for applications
requiring the highest possible dynamic performance.
To minimize system cost and power dissipation, the AD9054
includes an internal +2.5 V reference and track-and-hold circuit.
The user provides only a +5 V power supply and an encode
clock. No external reference or driver components are required
for many applications.
AIN
AIN
ENCODE
ENCODE
FUNCTIONAL BLOCK DIAGRAM
VREF IN
VREF OUT
AD9054
؉2.5V REFERENCE
T/H
TIMING
QUANTIZER
8
ENCODE
LOGIC
DEMULTIPLEXER 8
DA7 – D A0
DB7 – D B0
VDD GND
DEMUX
DS DS
The AD9054’s encode input interfaces directly to TTL, CMOS
or positive-ECL logic and will operate with single-ended or
differential inputs. The user may select dual-channel or single-
channel digital outputs. The dual (demultiplexed) mode inter-
leaves ADC data through two 8-bit channels at one-half the
clock rate. Operation in demultiplexed mode reduces the speed
and cost of external digital interfaces while allowing the ADC to
be clocked to the full 200 MSPS conversion rate. In the single-
channel (nondemultiplexed) mode, all data is piped at the full
clock rate to the Channel A outputs.
Fabricated with an advanced BiCMOS process, the AD9054 is
provided in a space-saving 44-lead TQFP surface mount plastic
package (ST-44) and specified over the full industrial (–40°C to
+85°C) temperature range.
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1997
1 page  
AD9054
SAMPLE N–1
SAMPLE N
SAMPLE N+3
SAMPLE N+4
AIN
ENCODE
ENCODE
tA
tEH
SAMPLE N+1
tEL 1/fS
SAMPLE N+2
tPD
tV
D7 – D 0
DATA N–5
DATA N–4
DATA N–3
DATA N–2
DATA N–1
DATA N
Figure 1. Timing—Single Channel Mode
SAMPLE N–1
SAMPLE N
AIN
SAMPLE N+3 SAMPLE N+4
SAMPLE N+5
SAMPLE N–2
ENCODE
tA
tEH tEL
1/fS
ENCODE
DS
DS
PORT A
D7 – D 0
tHDS
tSDS
tHDS
tSDS
DATA N–7
OR N–8
tPWDS
DATA N–7
OR N–6
SAMPLE N+1
SAMPLE N+2
tPD
INVALID IF OUT OF SYNC
DATA N–4 IF IN SYNC
tV
DATA N–2
SAMPLE N+6
DATA N
PORT B
D7 – D 0
DATA N–8
OR N–7
DATA N–6
OR N–7
INVALID IF OUT OF SYNC
DATA N–5 IF IN SYNC
DATA N–3
Figure 2. Timing—Dual Channel Mode
DATA N–1
DATA N+1
REV. 0
–5–
5 Page 
AD9054
2.502
2.501
2.500
2.499
2.498
–40 –20 0 20 40 60 80 100
TAMB – ؇C
Figure 33. Reference Voltage vs. Temperature
APPLICATION NOTES
THEORY OF OPERATION
The AD9054 combines Analog Devices’ patented MagAmp bit-
per-stage architecture with flash converter technology to create
a high performance, low power ADC. For ease of use the part
includes an onboard reference and input logic that accepts
TTL, CMOS or PECL levels.
The analog input signal is buffered by a high-speed differential
amplifier and applied to a track-and-hold (T/H) circuit. This
T/H captures the value of the input at the sampling instant and
maintains it for the duration of the conversion. The sampling
and conversion process is initiated by a rising edge on the
ENCODE input. Once the signal is captured by the T/H, the
four Most Significant Bits (MSBs) are sequentially encoded by
the MagAmp string. The residue signal is then encoded by a
flash comparator string to generate the four Least Significant
Bits (LSBs). The comparator outputs are decoded and com-
bined into the eight-bit result.
If the user has selected Single Channel Mode (DEMUX =
HIGH), the eight-bit data word is directed to the Channel A
output bank. Data are strobed to the output on the rising edge
of the ENCODE input with four pipeline delays. If the user has
selected Dual Channel Mode (DEMUX = LOW) the data are
alternately directed between the A and B output banks and have
five pipeline delays. At power-up, the N sample data can ap-
pear at either the A or B port. To align the data in a known
state the user must strobe DATA SYNC (DS, DS) per the
conditions described in the Timing section.
Graphics Applications
The high bandwidth and low power of the AD9054 make it
very attractive for applications that require the digitization of
presampled waveforms, wherein the input signal rapidly slews
from one level to another and is relatively stable for a period of
time. Examples of these include digitizing the output of com-
puter graphic display systems and very high speed solid state
imagers.
These applications require the converter to process inputs with
frequency components well in excess of the sampling rate (often
with subnanosecond rise times), after which the A/D must settle
and sample the input in well under one pixel time. The archi-
tecture of the AD9054 is vastly superior to older flash architec-
tures, which not only exhibit excessive input capacitance (which
is very hard to drive) but can make major errors when fed a very
rapidly slewing signal. The AD9054’s extremely wide bandwidth
Track/Hold circuit processes these signals without difficulty.
Using the AD9054
Good high speed design practices must be followed when using
the AD9054. To obtain maximum benefit, decoupling capaci-
tors should be physically as close to the chip as possible. We
recommend placing a 0.1 µF capacitor at each power-ground
pin pair (9 total) for high frequency decoupling, and including
one 10 µF capacitor for local low frequency decoupling. The
VREF IN pin should also be decoupled by a 0.1 µF capacitor.
The part should be located on a solid ground plane and output
trace lengths should be short (<1 inch) to minimize transmis-
sion line effects. This avoids the need for termination resistors
on the output bus and reduces the load capacitance that needs
to be driven, which in turn minimizes on-chip noise due to
heavy current flow in the outputs. We have obtained optimum
performance on our evaluation board by tying all VDD pins to a
quiet analog power supply system, and tying all GND pins to a
quiet analog system ground.
Minimum Encode Rate
The minimum sampling rate for the AD9054 is 25 MHz. To
achieve very high sampling rates, the track/hold circuit employs
a very small hold capacitor. When operated below the minimum
guaranteed sampling rate, the T/H droop becomes excessive.
This is first observed as an increase in offset voltage, followed by
degraded linearity at even lower frequencies.
Lower effective sampling rates may be easily supported by oper-
ating the converter in dual port output mode and using only one
output channel. A majority of the power dissipated by the AD9054
is static (not related to conversion rate) so the penalty for clock-
ing at twice the desired rate is not high.
Reference
The AD9054 internal reference, VREF, provides a simple, cost
effective reference for many applications. It exhibits reasonable
accuracy and excellent stability over power supply and tempera-
ture variations. The VREF OUT pin can simply be strapped to
the VREF IN pin. The internal reference can be used to drive
additional loads (up to several mA), including multiple A/D con-
verters as might be required in a triple video converter application.
When an external reference is desired for accuracy or other
requirements, the AD9054 should be driven directly by the
external reference source connected to pin VREF IN (VREF
OUT can be left floating). The external reference can be set to
2.5 V ± 0.25 V. If VREF IN is raised by 10% (set to 2.75 V) the
analog full-scale range will increase by 10% to 1.024 × 1.1 =
1.1264 V. The new input range will then be AIN ± 0.5632 V.
Digital Inputs
SNR performance is directly related to the sampling clock sta-
bility in A/D converters, particularly for high input frequencies
and wide bandwidths. A low jitter clock (<10 ps @ 100 MHz)
is essential for optimum performance when digitizing signals
that are not presampled.
ENCODE and Data Select (DS) can be driven differentially or
single-ended. For single-ended operation, the complement
inputs (ENCODE, DS) are internally biased to VDD/3 (~1.5 V)
by a high impedance on-chip resistor divider (Figure 5), but
they may be externally driven to establish an alternate threshold
if desired. A 0.1 µF decoupling capacitor to ground is sufficient
to maintain a threshold appropriate for TTL or CMOS logic.
REV. 0
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD9054.PDF ] | |
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