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PDF AD8842 Data sheet ( Hoja de datos )
| Número de pieza | AD8842 | |
| Descripción | CMOS TrimDAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Low Cost
Replaces 8 Potentiometers
50 kHz 4-Quadrant Multiplying Bandwidth
Low Zero Output Error
Eight Individual Channels
3-Wire Serial Input
500 kHz Update Data Loading Rate
±3 V Output Swing
Midscale Preset, Zero Volts Out
APPLICATIONS
Automatic Adjustment
Trimmer Replacement
Vertical Deflection Amplitude Adjustment
Waveform Generation and Modulation
8-Bit Octal, 4-Quadrant
Multiplying, CMOS TrimDAC
AD8842
FUNCTIONAL BLOCK DIAGRAM
VDD
LD
SDI
CLK
DECODED
ADDRESS
8
LOGIC
DATA
48
SERIAL
REGISTER
8X 8
DAC
R
E
G
I
S
T
E
R
S
8
8
DAC A
G
AD8842
DAC H
G
VINA
VOUT A
VINH
VOUT H
GND
SDO PR
VSS
GENERAL DESCRIPTION
The AD8842 provides eight general purpose digitally controlled
voltage adjustment devices. The TrimDAC® capability allows
replacement of the mechanical trimmer function in new designs.
The AD8842 is ideal for ac or dc gain control of up to 50 kHz
bandwidth signals. The four-quadrant multiplying capability is
useful for signal inversion and modulation often found in video
vertical deflection circuitry.
Internally the AD8842 contains eight voltage output digital-to-
analog converters, each with separate voltage inputs. A new
current conveyor amplifier design performs the four-quadrant
multiplying function with a single amplifier at the output of the
current steering digital-to-analog converter. This approach of-
fers an improved constant input resistance performance versus
previous voltage switched DACs used in TrimDAC circuits,
eliminating the need for additional input buffer amplifiers.
Each DAC has its own DAC register that holds its output state.
These DAC registers are updated from an internal serial-to-
parallel shift register that is loaded from a standard 3-wire serial
input digital interface. Twelve data bits make up the data word
clocked into the serial input register. This data word is decoded
where the first 4 bits determine the address of the DAC register
to be loaded with the last 8 bits of data. A serial data output pin
at the opposite end of the serial register allows simple daisy
chaining in multiple DAC applications without additional exter-
nal decoding logic.
TrimDAC is a registered trademark of Analog Devices, Inc.
The current conveyor amplifier is a patented circuit belonging to Analog
Devices, Inc.
The AD8842 consumes only 95 mW from ± 5 V power supplies.
For single 5 V supply applications consult the DAC-8841. The
AD8842 is pin compatible with the 1 MHz multiplying band-
width DAC8840. The AD8842 is available in 24-pin plastic
DIP and surface mount SOL-24 packages.
RR
VIN
VOUT
VOUT = VIN • (D/128 – 1)
Figure 1. Functional Circuit of One 4-Quadrant
Multiplying Channel
VIN REF
R
D VIN
256 R
(1- D) VIN
256 R
CURRENT CONVEYOR
AMPLIFIER
I1
VOUT
= VIN (D/128–1)
I2
R
Figure 2. Actual Current Conveyor Implementation of
Multiplying DAC Channel
REV. A
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 781/329-4700
Fax: 781/461-3113
1 page  
VOUTC 1
24 VOUTD
VOUTB 2
23 VINC
VOUTA 3
22 VIND
VINB 4
21 VDD
VINA 5
20 SDI
GND 6 AD8842 19 VSS
PR
7
TOP VIEW
(Not to Scale)
18
SDO
VINE 8
17 CLK
VINF 9
16 LD
VOUTE 10
15 VINH
VOUTF 11
14 VING
VOUTG 12
13 VOUTH
5 Page 
AD8842
ADJUSTING AC OR DC SIGNAL LEVELS
The four-quadrant multiplication operation of the AD8842 is
shown in Figure 27. For dc operation the equation describing
the relationship between VIN, digital inputs and VOUT is:
VOUT(D) = (D/128-1) × VIN
(1)
where D is a decimal number between 0 and 255
The actual output voltages generated with a fixed 3 V dc input
applied to VIN are summarized in this table.
Table III.
Decimal
Input (D)
0
1
127
128
129
254
255
VOUT(D)
–3.00 V
–2.98
–0.02
0.00
0.02
2.95
2.98
Comments
(VIN = 3 V)
Inverted FS
Zero Output
Full Scale (FS)
Notice that the output polarity is the same as the input polarity
when the DAC register is loaded with 255 (in binary = all ones).
Also note that the output does not exactly equal the input volt-
age. This is a result of the R-2R ladder DAC architecture cho-
sen. When the DAC register is loaded with 0, the output
polarity is inverted and exactly equals the magnitude of the in-
put voltage VIN. The actual voltage measured when setting up a
DAC in this example will vary within the ±1 LSB linearity error
specification of the AD8842. The calculated voltage error would
be ±0.023 V (= ± 3 V/128).
If VIN is an ac signal such as a sine wave, then we can use Equa-
tion 2 to describe circuit performance.
VOUT (t, D) = (D/128-1) × A sin (ωt)
(2)
where ω = 2 πf, A = sine wave amplitude, and D = decimal
input code.
This transfer characteristic Equation 2 lends itself to amplitude
and phase control of the incoming signal VIN. When the DAC is
loaded with all zeros, the output sine wave is shifted by 180°
with respect to the input sine wave. This powerful multiplying
capability can be used for a wide variety of modulation, wave-
form adjustment and amplitude control.
SIGNAL INPUTS (VINA, B, C, D, E, F, G, H)
The eight independent VIN inputs have a constant input-
resistance nominal value of 19 kΩ as specified in the electrical
characteristics table. These signal-inputs are designed to receive
not only dc, but ac input voltages. The signal-input voltage
range can operate to within one volt of either supply. That is,
the operating input-voltage-range is:
VSS + 1 V < VINx < (VDD – 1 V)
(3)
DAC OUTPUTS (VOUTA, B, C, D, E, F, G, H)
The eight D/A converter outputs are fully buffered by the
AD8842’s internal amplifier. This amplifier is designed to drive
up to 1 kΩ loads in parallel with 100 pF. However, in order to
minimize internal device power consumption, it is recom-
mended whenever possible to use larger values of load resis-
tance. The amplifier output stage can handle shorts to GND;
however, care should be taken to avoid continuous short circuit
operation.
The low output impedance of the buffers minimizes crosstalk
between analog input channels. A graph (Figure 11) of analog
crosstalk between channels is provided in the typical perfor-
mance characteristics section. At 100 kHz 70 dB of channel-to-
channel isolation exists. It is recommended to use good circuit
layout practice such as guard traces between analog channels
and power supply bypass capacitors. A 0.01 µF ceramic in paral-
lel with a 1 µF–10 µF tantalum capacitor provides a good power
supply bypass for most frequencies encountered.
DIGITAL INTERFACING
The four digital input pins (CLK, SDI, LD, PR) of the AD8842
were designed for TTL and 5 V CMOS logic compatibility. The
SDO output pin offers good fanout in CMOS logic applications
and can easily drive several AD8842s.
The Logic Contro Input Truth Table II describes how to shift
data into the internal 12-bit serial input register. Note that the
CLK is a positive-edge sensitive input. If mechanical switches
are used for breadboard evaluation, they should be debounced
by a flipflop or other suitable means. The basic three-wire serial
data interface setup is shown in Figure 30.
ZERO VOLTAGE
OUTPUT PRESET
SERIAL DATA
CLOCK
LOAD STROBE
7 PR
21 +5V
AD8842
20 SDI
17 CLK
6
16 LD
19 –5V
Figure 30. Basic Three-Wire Serial Interface
The required address plus data input format is defined in the se-
rial input decode Table I. Note there are 8 address states that
result in no operation (NOP) or activity in the AD8842 when
the positive edge triggered load-strobe (LD) is activated. This
NOP can be used in cascaded applications where only one DAC
out of several packages needs updating. The packages not re-
quiring data changes would receive the NOP address, that is, all
zeros. It takes 12 clocks on the CLK pin to fully load the serial-
input shift-register. Data on the SDI input pin is subject to the
timing diagram (Figure 3) data setup and data hold time re-
quirements. After the twelfth clock pulse the processor needs to
activate the LD strobe to have the AD8842 decode the serial-
register contents and update the target DAC register with the 8-
bit data word. This needs to be done before the thirteenth
positive clock edge. The timing requirements are provided in
the electrical characteristic table and in the Figure 3 timing dia-
gram. After twelve clock edges, data initially loaded into the
shift register at SDI appears at the shift register output SDO. A
multiple package interface circuit is shown in Figure 31. In this
topology all the devices are clocked with the new data; however,
only the decoded package address signal updates the target
package LD strobe which is being used as a chip select.
–10–
REV. A
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| Páginas | Total 14 Páginas | |
| PDF Descargar | [ Datasheet AD8842.PDF ] | |
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