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PDF AD8582 Data sheet ( Hoja de datos )
| Número de pieza | AD8582 | |
| Descripción | +5 Volt/ Parallel Input Complete Dual 12-Bit DAC | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
Complete Dual 12-Bit DAC
No External Components
Single +5 Volt Operation
1 mV/Bit with 4.095 V Full Scale
True Voltage Output, ±5 mA Drive
Very Low Power: 5 mW
APPLICATIONS
Digitally Controlled Calibration
Portable Equipment
Servo Controls
Process Control Equipment
PC Peripherals
GENERAL DESCRIPTION
The AD8582 is a complete, parallel input, dual 12-bit, voltage
output DAC designed to operate from a single +5 volt supply.
Built using a CBCMOS process, this monolithic DAC offers the
user low cost, and ease-of-use in +5 volt only systems.
Included on the chip, in addition to the DACs, are a rail-to-rail
amplifier, latch and reference. The reference (VREF) is trimmed
to 2.5 volts output, and the on-chip amplifier gains up the DAC
output to 4.095 volts full scale. The user needs only supply a +5
volt supply.
The AD8582 is coded natural binary. The op amp output
swings from 0 volt to +4.095 volts for a one-millivolt-per-bit
resolution, and is capable of driving ± 5 mA. Operation down to
4.3 V is possible with output load currents less than 1 mA.
5.0
∆∆VFS ≤ 1 LSB
DATA = FFFH
4.8 TA = +25°C
4.6
PROPER OPERATION
WHEN VDD SUPPLY
4.4 VOLTAGE ABOVE
CURVE
4.2
4.0
0.01
0.1 1.0 10
OUTPUT LOAD CURRENT – mA
100
Figure 1. Minimum Supply Voltage vs. Load
+5 Volt, Parallel Input
Complete Dual 12-Bit DAC
AD8582
FUNCTIONAL BLOCK DIAGRAM
AD8582
12
LDA
DAC A
REGISTER
12-BIT
DAC A
VDD
VOUTA
CS
A/B
DATA
LDB
INPUT A
REGISTER
12 2
INPUT B
REGISTER
REFERENCE
DAC B
REGISTER
12
12-BIT
DAC B
DGND
RST MSB
VREF
VOUTB
AGND
The high speed parallel data interface connects to the fastest
processors without wait states. The double-buffered input struc-
ture allows the user to load the input registers one at a time,
then a single load strobe tied to both LDA + LDB inputs will
update both DAC outputs simultaneously. LDA and LDB can
also be activated independently to immediately update their re-
spective DAC registers. An address input decodes DAC A or
DAC B when the chip select CS input is strobed. An asynchro-
nous reset input sets the output to zero scale. The MSB bit can
be used to establish a preset to midscale when the reset input is
strobed.
The AD8582 is available in the 24-pin plastic DIP and the sur-
face mount SOIC-24. Each part is fully specified for operation
over –40°C to +85°C, and the full +5 V ± 5% power supply
range.
2.0
1.5
1.0
0.5
0.0
–0.5
–1.0
–1.5
–2.0
0
VDD = +5V
TA = –55°C, +25°C, +85°C
= +25°C & +85°C
= –55°C
1024
2048
3072
4096
DIGITAL INPUT CODE – Decimal
Figure 2. Linearity Error vs. Digital Code and Temperature
REV. 0
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood. MA 02062-9106, U.S.A.
Tel: 617/329-4700
Fax: 617/326-8703
1 page  
AD8582
Figures 5 and 6 in the typical performance characteristics sec-
tion provide information on output swing performance near
ground and full-scale as a function of load. In addition to resis-
tive load driving capability, the amplifier has also been carefully
designed and characterized for up to 500 pF capacitive load
driving capability.
REFERENCE SECTION
The internal 2.5 V curvature-corrected bandgap voltage refer-
ence is laser trimmed for both initial accuracy and low tempera-
ture coefficient. The voltage generated by the reference is
available at the VREF pin. Since VREF is not intended to drive ex-
ternal loads, it must be buffered. The equivalent emitter fol-
lower output circuit of the VREF pin is shown in Figure 3.
Bypassing the VREF pin will improve noise performance; how-
ever, bypassing is not required for proper operation. Figure 8
shows broadband noise performance.
POWER SUPPLY
The very low power consumption of the AD8582 is a direct re-
sult of a circuit design optimizing use of the CBCMOS process.
By using the low power characteristics of the CMOS for the
logic, and the low noise, tight matching of the complementary
bipolar transistors good analog accuracy is achieved.
For power-consumption sensitive applications it is important to
note that the internal power consumption of the AD8582 is
strongly dependent on the actual logic-input voltage levels
present on the DB0–DB11, CS, A/B, MSB, LDA, LDB and
RST pins. Since these inputs are standard CMOS logic struc-
tures they contribute static power dissipation dependent on the
actual driving logic VOH and VOL voltage levels. The graph in
Figure 9 shows the effect on total AD8582 supply current as a
function of the actual value of input logic voltage. Conse-
quently, for optimum dissipation use of CMOS logic versus
TTL provides minimal dissipation in the static state. A VINL =
0 V on the DB0–11 pins provides the lowest standby dissipation
of 1 mA typical with a +5 V power supply.
As with any analog system, it is recommended that the AD8582
power supply be bypassed on the same PC card that contains
the chip. Figure 10 shows the power supply rejection versus fre-
quency performance. This should be taken into account when
using higher frequency switched-mode power supplies with
ripple frequencies of 100 kHz and higher.
One advantage of the rail-to-rail output amplifiers used in the
AD8582 is the wide range of usable supply voltage. The part is
fully specified and tested over temperature for operation from
+4.75 V to +5.25 V. If reduced linearity and source current
capability near full scale can be tolerated, operation of the
AD8582 is possible down to +4.3 volts. The minimum operat-
ing supply voltage versus load current plot, in Figure 1, pro-
vides information for operation below VDD = +4.75 V.
TIMING AND CONTROL
The input registers are level triggered and acquire data from the
data bus during the time period when CS is low. The input reg-
ister selected is determined by the A/B select pin, see Table I.
for a complete description. When CS goes high, the data is
latched into the register and held until CS returns low. The
minimum time required for the data to be present on the bus
before CS returns high is called the data setup time (tDS) as seen
in Timing Diagram. The data hold time (tDH) is the amount
of time that the data has to remain on the bus after CS goes
high. The high speed timing offered by the AD8582 provides
for direct interface with no wait states in all but the fastest
microprocessors.
The data from the input registers is transferred to the DAC reg-
isters by the active low LDA and LDB pins. If these inputs are
tied together, a single logic input can perform a double buffer
update of the DAC registers, which in turn simultaneously
changes the analog output voltages to a new value. If the LDA
and LDB pins are wired low, they become transparent. In this
mode the input register data will directly control the output
voltages. Refer to the Control Logic Truth Table for a com-
plete description.
Unipolar Output Operation
This is the basic mode of operation for the AD8582. The
AD8582 has been designed to drive loads as low as 820Ω in par-
allel with 500 pF. The code table for this operation is shown in
Table II.
Table II. Unipolar Code Table
Hexadecimal
Number in DAC
Register
FFF
801
800
7FF
000
Decimal Number
in DAC Register
4095
2049
2048
2047
0
Analog Output
Voltage (V)
+ 4.095
+ 2.049
+ 2.048
+ 2.047
0
REV. 0
–5–
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