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PDF AD8402 Data sheet ( Hoja de datos )
| Número de pieza | AD8402 | |
| Descripción | 2-Channel/ 256-Position Digital Potentiometer | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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FEATURES
256-position variable resistance device
Replaces 1, 2, or 4 potentiometers
1 kΩ, 10 kΩ, 50 kΩ, 100 kΩ
Power shutdown—less than 5 μA
3-wire,SPI-compatible serial data input
10 MHz update data loading rate
2.7 V to 5.5 V single-supply operation
Qualified for automotive applications
APPLICATIONS
Mechanical potentiometer replacement
Programmable filters, delays, time constants
Volume control, panning
Line impedance matching
Power supply adjustment
GENERAL DESCRIPTION
The AD8400/AD8402/AD8403 provide a single-, dual-, or
quad-channel, 256-position, digitally controlled variable resistor
(VR) device.1 These devices perform the same electronic adjust-
ment function as a mechanical potentiometer or variable
resistor. The AD8400 contains a single variable resistor in the
compact SOIC-8 package. The AD8402 contains two independent
variable resistors in space-saving SOIC-14 surface-mount
packages. The AD8403 contains four independent variable
resistors in 24-lead PDIP, SOIC, and TSSOP packages. Each
part contains a fixed resistor with a wiper contact that taps the
fixed resistor value at a point determined by the digital code
loaded into the controlling serial input register. The resistance
between the wiper and either endpoint of the fixed resistor
varies linearly with respect to the digital code transferred into
the VR latch. Each variable resistor offers a completely
programmable value of resistance between the A terminal and
the wiper or the B terminal and the wiper. The fixed A-to-B
terminal resistance of 1 kΩ, 10 kΩ, 50 kΩ, or 100 kΩ has a ±1%
channel-to-channel matching tolerance with a nominal
temperature coefficient of 500 ppm/°C. A unique switching
circuit minimizes the high glitch inherent in traditional
switched resistor designs, avoiding any make-before-break
or break-before-make operation.
(continued on Page 3)
1 The terms digital potentiometer, VR, and RDAC are used interchangeably.
Rev. E
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarksandregisteredtrademarksarethepropertyoftheirrespectiveowners.
1-/2-/4-Channel
Digital Potentiometers
AD8400/AD8402/AD8403
FUNCTIONAL BLOCK DIAGRAM
VDD
DGND
SDI
CLK
CS
AD8403
DAC
SELECT
1
2
3
A1, A0 4
2
10-BIT
SERIAL 8
LATCH
D
CK Q RS
8-BIT 8 RDAC1
LATCH
CK RS
SHDN
RDAC2
8-BIT 8
LATCH
CK RS
SHDN
RDAC3
8-BIT 8
LATCH
CK RS
SHDN
RDAC4
8-BIT 8
LATCH
CK RS
SHDN
A1
W1
B1
AGND1
A2
W2
B2
AGND2
A3
W3
B3
AGND3
A4
W4
B4
AGND4
SDO
RS SHDN
Figure 1.
100
RWA
75
RWB
50
25
0
0 64 128 192 255
CODE (Decimal)
Figure 2. RWA and RWB vs. Code
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
© 2010 Analog Devices, Inc. All rights reserved.
1 page  
AD8400/AD8402/AD8403
Parameter
DYNAMIC CHARACTERISTICS6, 10
Bandwidth −3 dB
Total Harmonic Distortion
VW Settling Time
Resistor Noise Voltage
Crosstalk 11
Symbol Conditions
BW_10 K
THDW
tS
eNWB
CT
R = 10 kΩ
VA = 1 V rms + 2 V dc, VB = 2 V dc, f = 1 kHz
VA = VDD, VB = 0 V, ±1% error band
RWB = 5 kΩ, f = 1 kHz, RS = 0
VA = VDD, VB = 0 V
Min
Typ1 Max Unit
600
0.003
2
9
−65
kHz
%
μs
nV/√Hz
dB
1 Typical represents average readings at 25°C and VDD = 5 V.
2 Resistor position nonlinearity error R-INL is the deviation from an ideal value measured between the maximum resistance and the minimum resistance wiper
positions. R-DNL measures the relative step change from ideal between successive tap positions. Parts are guaranteed monotonic. See the test circuit in Figure 38.
IW = 50 μA for VDD = 3 V and IW = 400 μA for VDD = 5 V for the 10 kΩ versions.
3 VAB = VDD, wiper (VW) = no connect.
4 INL and DNL are measured at VW with the RDAC configured as a potentiometer divider similar to a voltage output D/A converter. VA = VDD and VB = 0 V.
DNL specification limits of ±1 LSB maximum are guaranteed monotonic operating conditions. See the test circuit in Figure 37.
5 Resistor Terminal A, Resistor Terminal B, and Resistor Terminal W have no limitations on polarity with respect to each other.
6 Guaranteed by design and not subject to production test. Resistor-terminal capacitance tests are measured with 2.5 V bias on the measured terminal. The remaining
resistor terminals are left open circuit.
7 Measured at the Ax terminals. All Ax terminals are open-circuited in shutdown mode.
8 Worst-case supply current is consumed when the input logic level is at 2.4 V, a standard characteristic of CMOS logic. See Figure 28 for a plot of IDD vs. logic voltage.
9 PDISS is calculated from (IDD × VDD). CMOS logic level inputs result in minimum power dissipation.
10 All dynamic characteristics use VDD = 5 V.
11 Measured at a VW pin where an adjacent VW pin is making a full-scale voltage change.
Rev. E | Page 5 of 32
5 Page 
ABSOLUTE MAXIMUM RATINGS
TA = 25°C, unless otherwise noted.
Table 5.
Parameter
VDD to GND
VA, VB, VW to GND
Maximum Current
IWB, IWA Pulsed
IWB Continuous (RWB ≤ 1 kΩ, A Open)1
IWA Continuous (RWA ≤ 1 kΩ, B Open)1
IAB Continuous (RAB = 1 kΩ/10 kΩ/
50 kΩ/100 kΩ)1
Digital Input and Output Voltage
to GND
Operating Temperature Range
Maximum Junction Temperature
(TJ Maximum)
Storage Temperature
Lead Temperature (Soldering, 10 sec)
Package Power Dissipation
Thermal Resistance (θJA)
SOIC (R-8)
PDIP (N-14)
PDIP (N-24)
SOIC (R-14)
SOIC (R-24)
TSSOP-14 (RU-14)
TSSOP-24 (RU-24)
Rating
−0.3 V, +8 V
0 V, VDD
±20 mA
±5 mA
±5 mA
±2.1 mA/±2.1 mA/
±540 μA/±540 μA
0 V, 7 V
−40°C to +125°C
150°C
−65°C to +150°C
300°C
(TJ max − TA)/θJA
158°C/W
83°C/W
63°C/W
120°C/W
70°C/W
180°C/W
143°C/W
1 Maximum terminal current is bounded by the maximum applied voltage
across any two of the A, B, and W terminals at a given resistance, the maximum
current handling of the switches, and the maximum power dissipation of the
package; VDD = 5 V.
AD8400/AD8402/AD8403
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.
SERIAL DATA-WORD FORMAT
Table 6.
ADDR
DATA
B9 B8 B7 B6 B5 B4 B3 B2 B1 B0
A1 A0 D7 D6 D5 D4 D3 D2 D1 D0
MSB LSB MSB
29 28 27
LSB
20
ESD CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily accumulate on the
human body and test equipment and can discharge without detection. Although this product features
proprietary ESD protection circuitry, permanent damage may occur on devices subjected to high energy
electrostatic discharges. Therefore, proper ESD precautions are recommended to avoid performance
degradation or loss of functionality.
Rev. E | Page 11 of 32
11 Page | ||
| Páginas | Total 30 Páginas | |
| PDF Descargar | [ Datasheet AD8402.PDF ] | |
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