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PDF AD8381 Data sheet ( Hoja de datos )
| Número de pieza | AD8381 | |
| Descripción | 6-Channel Output DecDriver Decimating LCD Panel Driver | |
| Fabricantes | Analog Devices | |
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a Fast, High Voltage Drive, 6-Channel Output
DecDriver® Decimating LCD Panel Driver
AD8381
FEATURES
High Voltage Drive:
Rated Settling Time to within 1.3 V of Supply Rails
Output Overload Protection
High Update Rates:
Fast, 100 Ms/s 10-Bit Input Word Rate
Low Power Dissipation: 570 mW
Includes STBY Function
Voltage Controlled Video Reference (Brightness) and
Full-Scale (Contrast) Output Levels
3.3 V or 5 V Logic and 9 V to 18 V Analog Supplies
High Accuracy:
Laser Trimming Eliminates External Calibration
Flexible Logic:
INV Reverses Polarity of Video Signal
STSQ/XFR for Parallel AD8381 Operation in
12-Channel Systems
Drives Capacitive Loads:
27 ns Settling Time to 1% into 150 pF Load
Slew Rate 265 V/s with 150 pF Load
Available in 48-Lead LQFP
APPLICATIONS
LCD Analog Column Driver
FUNCTIONAL BLOCK DIAGRAM
DB (0:9)
STBY
BYP
E/O
R/L
CLK
STSQ
XFR
10 10
10
2-STAGE
LATCH
DAC
AD8381
10 10
2-STAGE
LATCH
DAC
BIAS
10 10
2-STAGE
LATCH
DAC
10 10
2-STAGE
LATCH
DAC
10 10
2-STAGE
LATCH
DAC
SEQUENCE
CONTROL
10 10
2-STAGE
LATCH
DAC
SCALING
CONTROL
VID0
VID1
VID2
VID3
VID4
VID5
VREFHI VREFLO
INV VMID
PRODUCT DESCRIPTION
The AD8381 provides a fast, 10-bit latched decimating digital
input, which drives six high voltage outputs. Ten-bit input
words are sequentially loaded into six separate high speed, bipolar
DACs. Flexible digital input format allows several AD8381s to be
used in parallel for higher resolution displays. STSQ synchronizes
sequential input loading, XFR controls synchronous output
updating and R/L controls the direction of loading as either
left-to-right or right-to-left. Six channels of high voltage
output drivers drive to within 1.3 V of the rail in rated settling
time. The output signal can be adjusted for brightness, signal
inversion, and contrast for maximum flexibility.
The AD8381 is fabricated on ADI’s proprietary, fast bipolar
24 V process, providing fast input logic, bipolar DACs with
trimmed accuracy and fast settling, high voltage precision drive
amplifiers on the same chip.
The AD8381 dissipates 570 mW nominal static power. The
STBY pin reduces power to a minimum, with fast recovery.
The AD8381 is offered in a 48-lead 7 mm ¥ 7 mm ¥ 1.4 mm
LQFP package and operates over the commercial temperature
range of 0∞C to 85∞C.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices. Trademarks and
registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700
www.analog.com
Fax: 781/326-8703 © 2003 Analog Devices, Inc. All rights reserved.
1 page  
AD8381
ABSOLUTE MAXIMUM RATINGS1
Supply Voltages
AVCCx – AGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 V
DVCC – DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5.5 V
Input Voltages
Maximum Digital Input Voltages . . . . . . . . DVCC + 0.5 V
Minimum Digital Input Voltages . . . . . . . . DGND – 0.5 V
Maximum Analog Input Voltages . . . . . . . . . AVCC + 0.5 V
Minimum Analog Input Voltages . . . . . . . . AGND – 0.5 V
Internal Power Dissipation2
LQFP Package @ 25∞C Ambient . . . . . . . . . . . . . . . . 2.7 W
Output Short Circuit Duration . . . . . . . . . . . . . . . . . . Infinite
Operating Temperature Range . . . . . . . . . . . . . . 0∞C to 85∞C
Storage Temperature Range . . . . . . . . . . . . –65∞C to +125∞C
Lead Temperature Range (Soldering 10 sec) . . . . . . . . 300∞C
NOTES
1Stresses above those listed under the Absolute Maximum Ratings may cause
permanent damage to the device. This is a stress rating only; functional operation
of the device at these or any other conditions above those indicated in the
operational section of this specification is not implied. Exposure to the absolute
maximum ratings for extended periods may reduce device reliability.
248-lead LQFP Package:
qJA = 45∞C/W (Still Air, 4-Layer PCB)
qJC = 19∞C/W
Overload Protection
The AD8381 employs a two-stage overload protection circuit
that consists of an output current limiter and a thermal shutdown.
The maximum current at any one output of the AD8381 is
internally limited to 100 mA average. In the event of a momen-
tary short circuit between a video output and a power supply rail
(VCC or AGND), the output current limit is sufficiently low to
provide temporary protection.
The thermal shutdown debiases the output amplifier when the
junction temperature reaches the internally set trip point. In the
event of an extended short circuit between a video output and a
power supply rail, the output amplifier current continues to
switch between 0 mA and 100 mA typ with a period determined by
the thermal time constant and the hysteresis of the thermal trip
point. The thermal shutdown provides long term protection by
limiting the average junction temperature to a safe level.
Recovery from a momentary short circuit is fast, approximately
100 ns. Recovery from a thermal shutdown is slow and is
dependent on the ambient temperature.
MAXIMUM POWER DISSIPATION
The maximum power that can be safely dissipated by the AD8381
is limited by its junction temperature. The maximum safe junc-
tion temperature for plastic encapsulated devices is determined
by the glass transition temperature of the plastic, approximately
150∞C. Exceeding this limit temporarily may cause a shift in the
parametric performance due to a change in the stresses exerted
on the die by the package. Exceeding a junction temperature of
175∞C for an extended period can result in device failure.
To ensure proper operation within the specified operating tem-
perature range, it is necessary to limit the maximum power
dissipation as follows:
PDMAX = (TJMAX – TA)/qJA
where:
TJMAX = 150∞C.
3.5
3.0
2.5
2.0
1.5
1.0
0.5
0
10 20 30 40 50 60 70 80 90
AMBIENT TEMPERATURE – ؇C
Figure 4. Maximum Power Dissipation vs. Temperature
Model
AD8381JST
AD8381-EB
ORDERING GUIDE
Temperature Package
Range
Description
Package
Option
0∞C to 85∞C 48-Lead LQFP ST-48
Evaluation Board
CAUTION
ESD (electrostatic discharge) sensitive device. Electrostatic charges as high as 4000 V readily
accumulate on the human body and test equipment and can discharge without detection. Although
the AD8381 features proprietary ESD protection circuitry, permanent damage may occur on
devices subjected to high-energy electrostatic discharges. Therefore, proper ESD precautions are
recommended to avoid performance degradation or loss of functionality.
–4– REV. B
5 Page 
AD8381
FUNCTIONAL DESCRIPTION
The AD8381 is a system building block designed to directly
drive the columns of LCD panels of the type popularized for use
in data projectors. It comprises six channels of precision 10-bit
digital-to-analog converters loaded from a single, high speed,
10-bit-wide input. Precision current feedback amplifiers, provid-
ing well-damped pulse response and rapid voltage settling into
large capacitive loads, buffer the six outputs. Laser trimming at
the wafer level ensure low absolute output errors and tight channel-
to-channel matching. In addition, tight part-to-part matching
in high channel count systems is guaranteed by the use of an
external voltage reference.
Input Data Loading (STart SeQuence Control—STSQ)
A valid STSQ control input initiates a new six-clock pulse
loading cycle, during which six input data words are loaded
sequentially into six internal channels. A new loading sequence
begins on the current active CLK edge only when STSQ was
held high at the preceding active CLK edge.
Data Loading—Expanded Systems (Even/Odd Control)
To facilitate expanded, even/odd systems, the active CLK edge, at
which input data is loaded, is set with the E/O control input.
Input data is loaded on rising CLK edges while the E/O input is
held high and loaded on falling CLK edges while the E/O input
is held low.
Data Loading—Inverted Images (Right/Left Control)
To facilitate image mirroring, the order in which input data is
loaded is set with the R/L input.
A new loading sequence begins at Channel 0 and proceeds
to Channel 5 when the R/L input is held high and begins at
Channel 5 and proceeding to Channel 0 when the R/L input
is held low.
Data Transfer to Outputs (XFR Control)
Data transfer to all outputs is initiated by the XFR control input.
When XFR is held high during a rising CLK edge, data is
simultaneously transferred to all outputs on the immediately
following falling CLK edge.
VCOM Reference (VMID Reference Input)
An external analog reference voltage connected to this input
sets the reference level at the outputs. This input is normally
connected to VCOM.
Full-Scale Output (VREFHI, VREFLO Reference Inputs)
The difference between two external analog reference voltages,
connected to these inputs, sets the full-scale output voltage at
the outputs. VREFLO is normally tied to VMID.
Analog Voltage Inversion (INVert Control)
To facilitate systems that use column, row or pixel inversion,
the analog output voltage inversion is controlled by the INV
control input. While INV is high, the analog voltage equivalent
of the input code is subtracted from (VMID + VFS) at each
output. While INV is low, the analog voltage equivalent of the
input code is added to (VMID – VFS) at each output.
Standby Mode (STBY Control)
A high applied to the STBY input debiases the internal
circuitry, dropping the quiescent power dissipation to a few
milliwatts. Since both digital and analog circuits are debiased,
all stored data will be lost. Upon returning STBY to low, nor-
mal operation is restored.
–10–
REV. B
11 Page | ||
| Páginas | Total 17 Páginas | |
| PDF Descargar | [ Datasheet AD8381.PDF ] | |
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