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What is AD8369?

This electronic component, produced by the manufacturer "Analog Devices", performs the same function as "45 dB Digitally Controlled VGA LF to 600 MHz".


AD8369 Datasheet PDF - Analog Devices

Part Number AD8369
Description 45 dB Digitally Controlled VGA LF to 600 MHz
Manufacturers Analog Devices 
Logo Analog Devices Logo 


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FEATURES
Digitally Controlled Variable Gain in 3 dB Steps
–5 dB to +40 dB (RL = 1 k)
–10 dB to +35 dB (RL = 200 )
Less than 0.2 dB Flatness over a +20 MHz Bandwidth
up to 380 MHz
4-Bit Parallel or 3-Wire Serial Interface
Differential 200 Input and Output Impedance
Single 3.0 V–5.5 V Supply
Draws 37 mA at 5 V
Power-Down <1 mA Maximum
APPLICATIONS
Cellular/PCS Base Stations
IF Sampling Receivers
Fixed Wireless Access
Wireline Modems
Instrumentation
45 dB Digitally Controlled VGA
LF to 600 MHz
AD8369
FUNCTIONAL BLOCK DIAGRAM
BIT3 BIT2 BIT1 BIT0
DENB
SENB
3dB STEP
GAIN CODE DECODE
BIAS
Gm CELLS
VPOS
PWUP
FILT
OPHI
OPLO
INHI
INLO
COMM
CMDC
COMM
PRODUCT DESCRIPTION
The AD8369 is a high performance digitally controlled variable
gain amplifier (VGA) for use from low frequencies to a –3 dB
frequency of 600 MHz at all gain codes. The AD8369 delivers
excellent distortion performance: the two-tone, third-order
intermodulation distortion is –69 dBc at 70 MHz for a 1 V p-p
composite output into a 1 kW load. The AD8369 has a nominal
noise figure of 7 dB when at maximum gain, then increases with
decreasing gain. Output IP3 is +19.5 dBm at 70 MHz into a
1 kW load and remains fairly constant over the gain range.
The signal input is applied to pins INHI and INLO. Variable gain
is achieved via two methods. The 6dB gain steps are implemented
using a discrete X-AMP® structure, in which the input signal is
palrsoogsreetsssitvheelyinapttuetniumapteeddabnycea; 2t0h0e 3WdRB-2stReplsadadreerimneptlwemoreknttehdata t
the output of the amplifier. This combination provides very
accurate 3dB gain steps over a span of 45 dB. The output imped-
ance is set by on-chip resistors across the differential output pins,
OPHI and OPLO. The overall gain depends upon the source
and load impedances due to the resistive nature of the input and
output ports.
Digital control of the AD8369 is achieved using either a serial or
a parallel interface. The mode of digital control is selected by
connecting a single pin (SENB) to ground or the positive sup-
ply. Digital control pins can be driven with standard CMOS
logic levels.
The AD8369 may be powered on or off by a logic level applied
to the PWUP pin. For a logic high, the chip powers up rapidly
to its nominal quiescent current of 37 mA at 25ºC. When low,
the total dissipation drops to less than a few milliwatts.
The AD8369 is fabricated on an Analog Devices proprietary, high
performance 25 GHz silicon bipolar IC process and is available
in a 16-lead TSSOP package for the industrial temperature range
of –40rC to +85rC. A populated evaluation board is available.
Rev. A
Document Feedback
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700 ©2015 Analog Devices, Inc. All rights reserved.
Technical Support
www.analog.com

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AD8369 equivalent
AD8369
SPECIFICATIONS (Continued)
Parameter
Frequency = 380 MHz
Voltage Gain
Gain Flatness
Noise Figure
Output IP3
IMD3
Harmonic Distortion
P1dB
Conditions
Within ± 20 MHz of 380 MHz
f1 = 379.55 MHz, f2 = 380.45 MHz
f1 = 379.55 MHz, f2 = 380.45 MHz,
VOPHI – VOPLO = 1 V p-p composite
Second-Order, VOPHI – VOPLO = 1 V p-p
Third-Order, VOPHI – VOPLO = 1 V p-p
For ± 1 dB deviation from linear gain
Specifications subject to change without notice.
Min
Typ
38.5
± 0.15
7.8
+8.5
+8.5
–47
–45
–49
+0.5
+0.5
Max Unit
dB
dB
dB
dBV rms
dBm
dBc
dBc
dBc
dBV rms
dBm
TIMING SPECIFICATIONS
SERIAL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25rC)
Parameter
Typ
Minimum Clock Pulsewidth (TPW)
Minimum Clock Period (TCK)
Minimum Setup Time Data vs. Clock (TDS)
Minimum Setup Time Data Enable vs. Clock (TES)
Minimum Hold Time Clock vs. Data Enable (TEH)
Minimum Hold Time Data vs. Clock (TDH)
10
20
2
2
2
4
PARALLEL PROGRAMMING TIMING REQUIREMENTS
(VS = 5 V, T = 25rC)
Parameter
Typ
Minimum Setup Time Data Enable vs. Data (TES)
Minimum Hold Time Data Enable vs. Data (TEH)
Minimum Data Enable Width (TPW)
2
2
4
Unit
ns
ns
ns
ns
ns
ns
Unit
ns
ns
ns
MSB
(BIT3)
DATA
(BIT 0)
CLOCK
(BIT 1)
TDS TDH
MSB
MSB–1
MSB–2
LSB
TPW
TCK
DATA
CLOCK
ENABLE DISABLED
(DENB)
TES
CLOCK
ENABLED
TEH
CLOCK
DISABLED
DATA IS LATCHED ON LOW-TO-HIGH TRANSITION OF DENB
(NOT TO SCALE)
Serial Programming Timing
MSB–1
(BIT2)
MSB–2
(BIT1)
LSB
(BIT0)
DENB
TES TEH
TPW
DATA IS LATCHED ON HIGH-TO-LOW
TRANSITION OF DENB
(NOT TO SCALE)
Parallel Programming Timing
–4– REV. A


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