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PDF AD8309 Data sheet ( Hoja de datos )
| Número de pieza | AD8309 | |
| Descripción | 5 MHz.500 MHz 100 dB Demodulating Logarithmic Amplifier with Limiter Output | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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a 5 MHz–500 MHz 100 dB Demodulating
Logarithmic Amplifier with Limiter Output
AD8309
FEATURES
Complete Multistage Log-Limiting IF Amplifier
100 dB Dynamic Range: –78 dBm to +22 dBm (Re 50 ⍀)
Stable RSSI Scaling Over Temperature and Supplies:
20 mV/dB Slope, –95 dBm Intercept
؎0.4 dB RSSI Linearity up to 200 MHz
Programmable Limiter Gain and Output Current
Differential Outputs to 10 mA, 2.4 V p-p
Overall Gain 100 dB, Bandwidth 500 MHz
Constant Phase (Typical ؎80 ps Delay Skew)
Single Supply of +2.7 V to +6.5 V at 16 mA Typical
Fully Differential Inputs, RIN = 1 k⍀, CIN = 2.5 pF
500 ns Power-Up Time, <1 A Sleep Current
APPLICATIONS
Receivers for Frequency and Phase Modulation
Very Wide Range IF and RF Power Measurement
Receiver Signal Strength Indication (RSSI)
Low Cost Radar and Sonar Signal Processing
Instrumentation: Network and Spectrum Analyzers
FUNCTIONAL BLOCK DIAGRAM
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
INHI
INLO
12dB
LADR ATTEN
4 ؋ DET
DET
12dB
DET
12dB
LIM
DET
BIAS
CTRL
LMHI
LMLO
LMDR
TEN DETECTORS SPACED 12dB
I-V VLOG
FLTR
ENBL
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
PRODUCT DESCRIPTION
The AD8309 is a complete IF limiting amplifier, providing both
an accurate logarithmic (decibel) measure of the input signal
(the RSSI function) over a dynamic range of 100 dB, and a
programmable limiter output, useful from 5 MHz to 500 MHz.
It is easy to use, requiring few external components. A single
supply voltage of +2.7 V to +6.5 V at 16 mA is needed, corre-
sponding to a power consumption of under 50 mW at 3 V, plus
the limiter bias current, determined by the application and
typically 2 mA, providing a limiter gain of 100 dB when using
200 Ω loads. A CMOS-compatible control interface can enable
the AD8309 within about 500 ns and disable it to a standby
current of under 1 µA.
The six cascaded amplifier/limiter cells in the main path have a
small signal gain of 12.04 dB (×4), with a –3 dB bandwidth of
850 MHz, providing a total gain of 72 dB. The programmable
output stage provides a further 18 dB of gain. The input is fully
differential and presents a moderately high impedance (1 kΩ in
parallel with 2.5 pF). The input-referred noise-spectral-density,
when driven from a terminated 50 Ω, source is 1.28 nV/√Hz,
equivalent to a noise figure of 3 dB. The sensitivity of the
AD8309 can be raised by using an input matching network.
Each of the main gain cells includes a full-wave detector. An
additional four detectors, driven by a broadband attenuator, are
used to extend the top end of the dynamic range by over 48 dB.
The overall dynamic range for this combination extends from
–91 dBV (–78 dBm at the 50 Ω level) to a maximum permissible
value of +9 dBV, using a balanced drive of antiphase inputs each
of 2 V in amplitude, which would correspond to a sine wave
power of +22 dBm if the differential input were terminated in
50 Ω. The slope of the RSSI output is closely controlled to
20 mV/dB, while the intercept is set to –108 dBV (–95 dBm
re 50 Ω). These scaling parameters are determined by a band-
gap voltage reference and are substantially independent of tem-
perature and supply. The logarithmic law conformance is typically
within ± 0.4 dB over the central 80 dB of this range at any fre-
quency between 10 MHz and 200 MHz, and is degraded only
slightly at 500 MHz.
The RSSI response time is nominally 67 ns (10%–90%). The
averaging time may be increased without limit by the addition of
an external capacitor. The full output of 2.34 V at the maximum
input of +9 dBV can drive any resistive load down to 50 Ω and
this interface remains stable with any value of capacitance on
the output.
The AD8309 is fabricated on an advanced complementary
bipolar process using silicon-on-insulator isolation techniques
and is available in the industrial temperature range of –40°C to
+85°C, in a 16-lead TSSOP package.
REV. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties
which may result from its use. No license is granted by implication or
otherwise under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781/329-4700 World Wide Web Site: http://www.analog.com
Fax: 781/326-8703
© Analog Devices, Inc., 1999
1 page  
2.5
2.0
1.5
1.0
TA = +85؇C
0.5
0
–100
TA = –40؇C
TA = +25؇C
–80 –60 –40
–20
0
20 40
INPUT LEVEL – dBm Re 50⍀
Figure 7. RSSI Output vs. Input Level, 100 MHz Sine Input,
at TA = –40°C, +25°C and +85°C, Single-Ended Input
AD8309
5
4
3
2
1 TA = +85؇C
0
–1
TA = +25؇C
–2
–3 TA = –40؇C
–4
–5
–100
–80
–60 –40
–20
0
20
40
INPUT LEVEL – dBm Re 50⍀
Figure 10. Log Linearity of RSSI Output vs. Input Level,
100 MHz Sine Input, at TA = –40°C, +25°C, and +85°C
2.5
100MHz
50MHz
200MHz
5MHz
2.0
1.5
1.0
0.5
0
–100 –80 –60 –40 –20
0
20 40
INPUT LEVEL – dBm Re 50⍀
Figure 8. RSSI Output vs. Input Level, at TA = +25°C, for
Frequencies of 5 MHz, 50 MHz, 100 MHz and 200 MHz
5
4
3 5MHz
2
DYNAMIC RANGE ؎1dB ؎3dB
5MHz
85 93
50MHz
91 99
100MHz
97 103
200MHz
96 102
1 50MHz
0
–1
100MHz 200MHz
–2
–3
–4
–5
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT LEVEL – dBm Re 50⍀
10 20 30
Figure 11. Log Linearity of RSSI Output vs. Input Level, at
TA = +25°C, for Frequencies of 5 MHz, 50 MHz, 100 MHz
and 200 MHz
2.5
300MHz
400MHz
2.0 500MHz
1.5
1.0
0.5
0
–100 –80 –60 –40 –20
0
20 40
INPUT LEVEL – dBm Re 50⍀
Figure 9. RSSI Output vs. Input Level, at TA = +25°C, for
Frequencies of 300 MHz, 400 MHz and 500 MHz
5
DYNAMIC RANGE ؎1dB ؎3dB
4
300MHz
90 102
400MHz
65 100
3
500MHz
66 100
2
1
300MHz
0
–1
–2 400MHz
500MHz
–3
–4
–5
–90 –80 –70 –60 –50 –40 –30 –20 –10 0
INPUT LEVEL – dBm Re 50⍀
10 20 30
Figure 12. Log Linearity of RSSI Output vs. Input Level,
at TA = +25°C, for Frequencies of 300 MHz, 400 MHz and
500 MHz
REV. B
–5–
5 Page 
AD8309
The total dynamic range of the AD8309, defined as the ratio
of the maximum permissible input to the noise floor, is thus
100 dB. Good accuracy is provided over a substantial part of
this range.
Input Matching
Monolithic log amps present a nominal input impedance much
higher than 50 Ω. For the AD8309, this can be modeled as 1 kΩ
shunted by 2.5 pF, at frequencies up to 300 MHz. Thus, a
simple input matching network can considerably improve the
basic sensitivity , when driving from a low-impedance source, by
increasing the voltage applied to the input. For a 50:1000 Ω
transformation, the voltage gain is 13 dB, and the whole dy-
namic range moves downward by this amount; that is, the inter-
cept is shifted to –121 dBV (–108 dBm at the primary 50 Ω
input). Note that while useful voltage gain is achieved in this
way, it does not follow that the noise-figure is minimal at the
optimum power match.
Offset Control
In a monolithic log amp, direct-coupling between the stages is
invariably utilized for practical reasons. Now, a dc offset voltage
in the early stages of the chain is indistinguishable from a “real”
signal. If as high as 400 µV, it would be 20 dB larger than the
smallest resolvable ac signal (40 µV), reducing the dynamic
range by this amount. This problem is solved by using a global
feedback path from the last stage to the first. The high-frequency
components of the signal must be removed; this achieved in the
AD8309 by an on-chip low-pass filter, providing sufficient sup-
pression of HF feedback to allow accurate operation down to at
least 5 MHz. Useful operation at lower frequencies remains
possible, although a particular device having a large dc offset will
exhibit a reduction in the low end region of the dynamic range.
PRODUCT OVERVIEW
The AD8309 is built on an advanced dielectrically-isolated
complementary bipolar process using thin-film resistor technol-
ogy for accurate scaling. It follows well-developed foundations
proven over a period of some fifteen years, with constant refine-
ment. The backbone of the AD8309 (Figure 25) comprises a
chain of six main amplifier/limiter stages, each having a gain of
12.04 dB (×4) and small-signal –3 dB bandwidth of 850 MHz.
The input interface at INHI and INLO (Pins 4 and 5) is fully
differential. Thus it may be driven from either single-sided or
balanced inputs, the latter being required at the very top end of
the dynamic range, where the total differential drive may be as
large as 4 V in amplitude.
The first six stages, also used in developing the logarithmic
RSSI output, are followed by a versatile programmable output,
and thus programmable gain, final limiter section. Its open-
collector outputs are also fully differential, at LMHI and LMLO
(Pins 12 and 13). This output stage provides a gain of 18 dB
when using equal valued load and bias setting resistors and the
pin-to-pin output is used. The overall voltage gain is thus 100 dB.
When using RLIM = RLOAD = 200 Ω, the additional current
consumption in the limiter is approximately 2.8 mA, of which
2 mA goes to the load. The ratio depends on RLIM (for example,
when 20 Ω, the efficiency is 90%), and the voltage at the pin
LMDR is rather more than 400 mV, but the total load current is
accurately (400 mV)/RLIM.
The rise and fall times of the hard-limited (essentially square-
wave) voltage at the outputs are typically 0.4 ns, when driven by
a sine wave input having an amplitude of 100 mV or greater,
and RLOAD = 50 Ω. The change in time-delay (“phase skew”)
over the input range –83 dBV (100 mV in amplitude, or –70 dBm
in 50 Ω) to –3 dBV (1 V or +10 dBm) is ±83 ps (±3° at 100 MHz).
SIX STAGES TOTAL GAIN 72dB
TYP GAIN 18dB
INHI
INLO
12dB
LADR ATTEN
4 ؋ DET
DET
12dB
DET
12dB
LIM
DET
BIAS
CTRL
LMHI
LMLO
LMDR
TEN DETECTORS SPACED 12dB
I-V VLOG
FLTR
ENBL
GAIN
BIAS
BAND-GAP
REFERENCE
SLOPE
BIAS
INTERCEPT
TEMP COMP
Figure 25. Main Features of the AD8309
The six main cells and their associated full-wave detectors,
having a transconductance (gm) form, handle the lower part of
the dynamic range. Biasing for these cells is provided by two
references, one of which determines their gain, the other being a
band-gap cell which determines the logarithmic slope, and stabi-
lizes it against supply and temperature variations. A special dc-
offset-sensing cell (not shown in Figure 25) is placed at the end
of this main section, and used to null any residual offset at the
input, ensuring accurate response down to the noise floor. The
first amplifier stage provides a short-circuited voltage-noise
spectral-density of 1.07 nV/√Hz.
The last detector stage includes a modification to temperature-
stabilize the log-intercept, which is accurately positioned so as to
make optimal use of the full output voltage range. Four further
“top end” detectors are placed at 12.04 dB taps along a passive
attenuator, to handle the upper part of the range. The differen-
tial current-mode outputs of all ten detectors stages are summed
with equal weightings and converted to a single-sided voltage by
the output stage, generating the logarithmic (or RSSI) output at
VLOG (Pin 16), nominally scaled 20 mV/dB (that is, 400 mV
per decade). The junction between the lower and upper regions
is seamless, and the logarithmic law-conformance is typically
well within ± 0.4 dB from –83 dBV to +7 dBV (–70 dBm to
+10 dBm).
The full-scale rise time of the RSSI output stage, which operates
as a two-pole low-pass filter with a corner frequency of 3.5 MHz, is
about 200 ns. A capacitor connected between FLTR (Pin 10)
and VLOG can be used to lower the corner frequency (see be-
low). The output has a minimum level of about 0.34 V (corre-
sponding to a noise power of –78 dBm, or 17 dB above the
nominal intercept of –95 dBm). This rather high baseline level
ensures that the pulse response remains unimpaired at very low
inputs.
The maximum RSSI output depends on the supply voltage and
the load. An output of 2.34 V, that is, 20 mV/dB × (12 + 105) dB,
is guaranteed when using a supply voltage of 4.5 V or greater
and a load resistance of 50 Ω or higher, for a differential input
of 9 dBV (a 4 V sine amplitude, using balanced drives). When
using a 3 V supply, the maximum differential input may still be
as high as –3 dBV (1 V sine amplitude), and the corresponding
RSSI output of 2.1 V, that is, 20 mV/dB × (0 + 105) dB is also
guaranteed.
REV. B
–11–
11 Page | ||
| Páginas | Total 20 Páginas | |
| PDF Descargar | [ Datasheet AD8309.PDF ] | |
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