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PDF AD8074 Data sheet ( Hoja de datos )
| Número de pieza | AD8074 | |
| Descripción | G = +1 and +2 Triple Video Buffers | |
| Fabricantes | Analog Devices | |
| Logotipo |  |
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Hay una vista previa y un enlace de descarga de AD8074 (archivo pdf) en la parte inferior de esta página. Total 15 Páginas | ||
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FEATURES
Dual Supply ؎5 V
High-Speed Fully Buffered Inputs and Outputs
600 MHz Bandwidth (–3 dB) 200 mV p-p
500 MHz Bandwidth (–3 dB) 2 V p-p
1600 V/s Slew Rate, G = +1
1350 V/s Slew Rate, G = +2
Fast Settling Time: 4 ns
Low Supply Current: <30 mA
Excellent Video Specifications (RL = 150 ⍀):
Gain Flatness of 0.1 dB to 50 MHz
0.01% Differential Gain Error
0.01؇ Differential Phase Error
“All Hostile“ Crosstalk
–80 dB @ 10 MHz
–50 dB @ 100 MHz
High “OFF” Isolation of 90 dB @ 10 MHz
Low Cost
Fast Output Disable Feature
APPLICATIONS
RGB Buffer in LCD and Plasma Displays
RGB Driver
Video Routers
500 MHz, G = +1 and +2 Triple
Video Buffers with Disable
AD8074/AD8075
FUNCTIONAL BLOCK DIAGRAM
AD8074 /AD8075
OE 1
16 VCC
DGND 2
IN2 3
G=
+1/+2
15 VCC
14 OUT2
AGND 4
IN1 5
G=
+1/+2
13 VEE
12 OUT1
AGND 6
IN0 7
G=
+1/+2
11 VCC
10 OUT0
VEE 8
9 VEE
PRODUCT DESCRIPTION
The AD8074/AD8075 are high-speed triple video buffers with
G = +1 and +2 respectively. They have a –3 dB full signal band-
width in excess of 450 MHz, along with slew rates in excess of
1400 V/µs. With better than –80 dB of all hostile crosstalk and
90 dB isolation, they are useful in many high-speed applica-
tions. The differential gain and differential phase error are 0.01%
and 0.01°. Gain flatness of 0.1 dB up to 50 MHz makes the
AD8074/AD8075 ideal for RGB buffering or driving. They
consume less than 30 mA on a ± 5 V supply.
Both devices offer a high-speed disable feature that allows the
outputs to be put into a high impedance state. This allows the
building of larger input arrays while minimizing “OFF” chan-
nel output loading. The AD8074/AD8075 are offered in a
16-lead TSSOP package.
Table I. Truth Table
OE OUT0, 1, 2
0 IN0, IN1, IN2
1 High Z
Rev. B
Information furnished by Analog Devices is believed to be accurate and
reliable. However, no responsibility is assumed by Analog Devices for its
use, nor for any infringements of patents or other rights of third parties that
may result from its use. No license is granted by implication or otherwise
under any patent or patent rights of Analog Devices.
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
www.analog.com
Fax: 781.461.3113
©2001–2011 Analog Devices, Inc. All rights reserved.
1 page  
0
VOUT = 2V p-p (ACTIVE CHANNEL(s))
–10 RL = 1k⍀
–20 RT = 37.5⍀
–30
–40
–50
–60
–70 ALL-HOSTILE
–80
–90 ADJACENT
–100
–110
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 7. AD8074 Crosstalk vs. Frequency (All Hostile and
Adjacent RL = 1 kΩ)
0
VOUT = 2V p-p
–10 RL = 150⍀
–20 RT = 37.5⍀
–30
–40
–50
SECOND
–60 HARMONIC
–70
–80 THIRD
HARMONIC
–90
–100
1
10 100
FUNDAMENTAL FREQUENCY – MHz
1000
TPC 8. AD8074 Distortion vs. Frequency
AD8074/AD8075
0
VOUT = 2V p-p (ACTIVE CHANNEL(s))
–10 RL = 150⍀
–20 RT = 37.5⍀
–30
–40
–50
–60 ALL-HOSTILE
–70
–80
ADJACENT
–90
–100
–110
0.1
1 10 100
FREQUENCY – MHz
1000
TPC 9. AD8075 Crosstalk vs. Frequency (All Hostile and
Adjacent RL = 150 Ω)
0
VOUT = 2V p-p
–10 RL = 150⍀
–20 RT = 37.5⍀
–30
–40
–50
–60
–70
–80
–90
–100
1
SECOND
HARMONIC
THIRD
HARMONIC
10 100
FUNDAMENTAL FREQUENCY – MHz
1000
TPC 10. AD8075 Distortion vs. Frequency
Rev. B
–5–
5 Page 
AD8074/AD8075
Triple Video Multiplexer
The AD8074 and AD8075 each have an output-enable function
that can be used to disable the outputs and put them in a high-
impedance state. Usually, for a unity-gain device, it is relatively
easy to provide high disabled impedance, because the feedback
path is from the output to a high-impedance input. However, for a
non-unity-gain part, the feedback provides a resistive path to
ground. This will usually dominate the disabled output imped-
ance, and make it a much lower value than the unity-gain device.
The AD8075 has an internal buffer that provides a low-impedance,
ground level output that terminates the feedback path during
enabled operation. In the disabled state, both this buffer output
and the amplifier output are disabled to a high impedance to
provide a high-impedance disabled state.
To construct a multiplexer, the outputs from one or more devices
are connected in parallel and only one device is enabled at a
time while all of the others are disabled. The two sets of inputs
are applied individually to each of the separate device inputs.
Figure 4 shows the circuit details for this function. The first RGB
Source 1 is input to the first AD8075. Each of the individual
signals is terminated to ground with 75 Ω to provide proper
termination for the input cables. In a similar fashion, the Source
2 signals are input to the second AD8075.
+5V +5V +5V
+
25F
0.1F
0.1F
0.1F
R
SOURCE 1 G
B
75⍀
75⍀
75⍀
AD8075
75⍀
75⍀
75⍀
OE
R
G OUTPUT
B
SEL1/SEL2
R
SOURCE 2 G
B
25F +
0.1F
0.1F
0.1F
–5V –5V –5V
+5V +5V +5V
+
25F
0.1F
0.1F
0.1F
OE
75⍀
75⍀
AD8075
75⍀
75⍀
75⍀
75⍀
Rev. B
25F +
0.1F
0.1F
0.1F
–5V –5V –5V
Figure 4. Mux
–11–
11 Page | ||
| Páginas | Total 15 Páginas | |
| PDF Descargar | [ Datasheet AD8074.PDF ] | |
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